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cyw4343x single-chip ieee 802.11 b/g/n mac/ baseband/radio with bluetooth 4.1, an fm receiver, and wireless charging cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document no. 002-14797 rev. *h revised october 19, 2016 the cypress cyw4343x is a highly integrated single-chip solution and offers the lowest rbom in the industry for smartphones smartphones wearables, tablets, and a wide r ange of other portable devices. the chip includes a 2.4 ghz wlan ieee 802.11 b/g/n mac/baseband/radio, bluetooth 4.1 support, and an fm receiver. in addition, it integrates a power amplifier (pa) that meets the out- put power requirements of most handheld syst ems, a low-noise amplifier (lna) for best- in-class receiver sensitivity, and an int ernal transmit/receive (itr) rf switch, fu rther reducing the overall solution cost and printed circuit board area. the wlan host interface supports gspi and sdio v2.0 modes, prov iding a raw data transfer rate up to 200 mbps when operating in 4-bit mode at a 50 mhz bus frequency. an independent, high-speed uart is provided for the blue tooth/fm host interface.using advanced design techniques and process technology to reduce active and idle power, the cyw4343x is designed to address the needs of highly mobile devices that require minimal power consum ption and compact size. it includes a power management unit tha t simplifies the system power topology and allows for operation directly from a rechargeable mobile platform battery while maximi zing battery life. the cyw4343x implements the world?s mo st advanced enhanced collaborative coexis tence algorithms and hardware mecha- nisms, allowing for an extremely collabor ative wlan and bluetooth coexistence. figure 1. cyw4343x system block diagram vddio vbat 2.4 ghz wlan + bluetooth tx/rx fm rx wlan host i/f bluetooth host i/f fm rx host i/f wl_reg_on sdio*/spi wl_irq bt_reg_on uart bt_dev_wake bt_host_wake bpf clk_req i 2 s pcm stereo analog out cyw4343x
document no. 002-14797 rev. *h page 2 of 128 cyw4343x figure 2. cyw4343x system block diagram vddio vbat 2.4 ghz wlan + bluetooth tx/rx fm rx cyw4343x wlan host i/f bluetooth host i/f fm rx host i/f wl_reg_on sdio*/spi wl_irq bt_reg_on uart bt_dev_wake bt_host_wake bpf clk_req pcm stereo analog out
document no. 002-14797 rev. *h page 3 of 128 cyw4343x features ieee 802.11x key features single-band 2.4 ghz ieee 802.11b/g/n. support for 2.4 ghz cypress turboqam? data rates (256-qam) and 20 mhz channel bandwidth. integrated itr switch supports a single 2.4 ghz antenna shared between wlan and bluetooth. supports explicit ieee 802.11n transmit beamforming tx and rx low-density parity check (ldpc) support for improved range and power efficiency. supports standard sdio v2.0 and gspi host inter- faces. supports space-time block coding (stbc) in the receiver. integrated arm cortex-m3 processor and on-chip memory for complete wlan subsystem functionality, minimizing the need to wake up the applications pro- cessor for standard wlan functions. this allows for further minimization of power consumption, while maintaining the ability to field-upgrade with future fea- tures. on-chip memory includes 512 kb sram and 640 kb rom. onedriver? software architecture for easy migration from existing embedded wlan and bluetooth devices as well as to future devices. bluetooth and fm key features complies with bluetooth core specification version 4.1 with provisions for suppor ting future specifications. bluetooth class 1 or class 2 transmitter operation. supports extended synchronous connections (esco), for enhanced voice quality by allowing for retransmission of dropped packets. adaptive frequency hopping (afh) for reducing radio frequency interference. interface support ? host c ontroller interface (hci) using a high-speed uart interface and pcm for audio data.bluetooth and fm key features (continued) fm receiver unit supports hci for communication. low-power consumption improv es battery life of hand- held devices. fm receiver: 65 mhz to 108 mhz fm bands; supports the european radio data systems (rds) and the north american radio broadcast data system (rbds) standards. supports multiple simult aneous advanced audio dis- tribution profiles (a2dp) for stereo sound. automatic frequency detection for standard crystal and tcxo values. general features supports a battery voltage range from 3.0v to 4.8v with an internal switching regulator. programmable dynamic power management. 4 kbit one-time programmable (otp) memory for storing board parameters. can be routed on low-cost 1 x 1 pcb stack-ups. 74-ball[4343w+43cs4343w1]74-ball 63-ball wlbga package (4.87 mm 2.87 mm, 0.4 mm pitch). 153-bump wlcsp package (115 m bump diameter, 180 m bump pitch). security: ? wpa and wpa2 (personal) support for powerful encryption and authentication. ? aes in wlan hardware for faster data encryption and ieee 802.11i compatibility. ? reference wlan subsystem provides cisco com- patible extensions (ccx, ccx 2.0, ccx 3.0, ccx 4.0, ccx 5.0). ? reference wlan subsystem provides wi?fi pro- tected setup (wps). worldwide regulatory support: global products sup- ported with worldwide homologated design. multimode wireless charging support that complies with the alliance for wireless power (a4wp), the wireless power consortium (wpc), and the power matters alliance (pma).
document no. 002-14797 rev. *h page 4 of 128 cyw4343x introduction this document provides details of the func tional, operational, and electrical characteristics of the cypress cyw4343x. it is in tended for hardware design, applic ation, and oem engineers. cypress part numbering scheme cypress is converting the acquired iot part numbers from broadcom to the cypress part numbering sch eme. due to this conversion, there is no change in form, fit, or function as a result of offering the device with cypress part number marking. the table pro vides cypress ordering part number that matches an existing iot part number. table 1. mapping table for part number between broadcom and cypress iot resources cypress provides a wealth of data at http://www.cypress.co m/internet-things-iot to help you to select the right iot device for your design, and quickly and effectively integrate the device into y our design. cypress provides cust omer access to a wide range of infor- mation, including technical documentation, schematic diagrams, product bill of materials, pcb layout information, and software updates. customers can acquire technical documentation and so ftware from the cypress s upport community website ( http://com- munity.cypress.com/ ). broadcom part number cypress part number bcm4343skubg CYW4343SKUBG bcm4343wkubg cyw4343wkubg bcm4343wkwbg cyw4343wkwbg bcm4343w1kubg cyw4343w1kubg
document no. 002-14797 rev. *h page 5 of 128 cyw4343x contents 1. overview ............................................................ 7 1.1 overview ............................................................. 7 1.2 features .............................................................. 9 1.3 standards compliance ........................................ 9 2. power supplies and power management ..... 11 2.1 power supply topology .. .............. ........... ......... 11 2.2 cyw4343x pmu features ............................... 11 2.3 wlan power management ............................... 18 2.4 pmu sequencing .............................................. 18 2.5 power-off shutdown ....... .................................. 19 2.6 power-up/power-down/re set circuits ............. 19 2.7 wireless charging ............................................. 19 3. frequency references ................................... 22 3.1 crystal interface and clock generation ............ 22 3.2 tcxo ................................................................ 22 3.3 external 32.768 khz low-power oscillator ....... 23 4. wlan system interfaces ............................... 25 4.1 sdio v2.0 .......................................................... 25 4.1.1 sdio pin descriptions ........................... 25 4.2 generic spi mode ............................................. 26 4.3 spi protocol ...................................................... 27 4.3.1 command structure .............................. 28 4.3.1.1.write ......................................................... 29 4.3.1.2.write/read ............................................... 29 4.3.1.3.read ........................................................ 29 4.3.2 status .................................................... 29 4.4 gspi host-device handshake ........................... 31 4.4.1 boot-up sequence . ........... ........... ......... 32 5. wireless lan mac and phy.......................... 35 5.1 mac features ................................................... 35 5.1.1 mac description ..... ............................... 35 5.1.1.1.psm ......................................................... 36 5.1.1.2.wep ......................................................... 36 5.1.1.3.txe .......................................................... 36 5.1.1.4.rxe .......................................................... 36 5.1.1.5.ifs ........................................................... 37 5.1.1.6.tsf .......................................................... 37 5.1.1.7.nav .......................................................... 37 5.1.1.8.mac-phy interface ................................. 37 5.2 phy description ................................................ 37 5.2.1 phy features ........................................ 37 6. wlan radio subsystem ................................ 39 6.1 receive path ..................................................... 39 6.2 transmit path .................................................... 40 6.3 calibration ......................................................... 40 7. bluetooth + fm subsystem overview........... 40 7.1 features .............................................................40 7.2 bluetooth radio ..................................................41 7.2.1 transmit ..................................................41 7.2.2 digital modulator ... ..................................41 7.2.3 digital demodulator and bit synchronizer ...........................................41 7.2.4 power amplifier ......................................42 7.2.5 receiver .................................................42 7.2.6 digital demodulator and bit synchronizer ...........................................42 7.2.7 receiver signal strength indicator .........42 7.2.8 local oscillator gener ation ...... ..............42 7.2.9 calibration ..............................................42 8. bluetooth baseband core.............................. 43 8.1 bluetooth 4.1 features .......................................43 8.2 link control layer .......... ....................................43 8.3 test mode support .............................................43 8.4 bluetooth power managemen t unit ..... ..............44 8.4.1 rf power management ..........................44 8.4.2 host controller power management ......44 8.5 bbc power management . ............... ........... ........45 8.5.1 fm power management .........................46 8.5.2 wideband speech ..................................46 8.6 packet loss concealment .................................46 8.6.1 codec encoding .....................................47 8.6.2 multiple simultaneous a2dp audio streams ........................................47 8.6.3 fm over bluetooth .................................47 8.7 adaptive frequency hopping .............................47 8.8 advanced bluetooth/wlan coexistence ...........47 8.9 fast connection (interlaced page and inquiry scans) ....................................................47 9. microprocessor and memory unit for bluetooth 48 9.1 ram, rom, and patch memory .........................48 9.2 reset ..................................................................48 10. bluetooth peripheral transport unit............. 48 10.1 pcm interface ....................................................48 10.1.1 slot mapping ......... ..................................48 10.1.2 frame synchronization ...........................48 10.1.3 data formatting ....... ...............................48 10.1.4 wideband speech support .....................49 10.1.5 multiplexed bluetooth and fm over pcm ................................................49 10.1.6 pcm interface timing .............................50 10.1.6.1.short frame sync, master mode ............50 10.1.6.2.short frame sync, slave mode ..............51 10.1.6.3.long frame sync, master mode .............52
document no. 002-14797 rev. *h page 6 of 128 cyw4343x 10.1.6.4.long frame sync, slave mode .............. 53 10.2 uart interface ................................................. 53 10.3 i 2 s interface ...................................................... 55 10.3.1 i 2 s timing .............................................. 55 11. fm receiver subsystem................................. 57 11.1 fm radio ........................................................... 57 11.2 digital fm audio interfaces ............................... 57 11.3 analog fm audio interfac es .............................. 57 11.4 fm over bluetooth ............................................ 57 11.5 esco ................................................................ 57 11.6 wideband speech link ... .............. ........... ......... 57 11.7 a2dp ................................................................. 58 11.8 autotune and search algo rithms ........ .............. 58 11.9 audio features .................................................. 58 11.10rds/rbds ....................................................... 60 12. cpu and global functions ............. ................ 61 12.1 wlan cpu and memory subsystem . .............. 61 12.2 one-time programmable memory .................... 61 12.3 gpio interface .................................................. 61 12.4 external coexistence in terface ......................... 61 12.4.1 2-wire coexistence ............................... 61 12.4.2 3-wire and 4-wire coexistence interfaces ............................................... 62 12.5 jtag interface ................................................. 63 12.6 uart interface ................................................ 63 13. wlan software architecture......................... 64 13.1 host software architectu re ............................... 64 13.2 device software architecture ............................ 64 13.3 remote downloader ....... .............. ........... ......... 64 13.4 wireless configuration utility ............................ 64 14. pinout and signal descriptions..................... 65 14.1 ball map ............................................................ 65 14.2 wlbga ball list in ball number order with x-y coordinates ................................................ 67 14.3 wlbga ball list in ball number order with x-y coordinates ................................................ 70 14.4 wlcsp bump list in bump order with x-y coordinates ................................................ 71 14.5 wlbga ball list ordered by ball name ........... 76 14.6 wlbga ball list ordered by ball name ........... 77 14.7 wlcsp bump list order ed by name .............. 78 14.8 signal descriptions ........................................... 80 14.9 wlan gpio signals and strapping options .... 87 14.10chip debug options .... ..................................... 87 14.11i/o states .......................................................... 88 15. dc characteristics.......................................... 91 15.1 absolute maximum rating s ...............................91 15.2 environmental ratings .......................................91 15.3 electrostatic discharge specifications ...............91 15.4 recommended operating conditions and dc characteristics .............................................92 16. wlan rf specifications................................ 93 16.1 2.4 ghz band general rf specifications ..........93 16.2 wlan 2.4 ghz receiver performance specifications .....................................................93 16.3 wlan 2.4 ghz transmitter performance specifications .....................................................96 16.4 general spurious emissions specifications .......97 17. bluetooth rf specifications .......................... 98 18. fm receiver specifications ......................... 104 19. internal regulator electrical specifications ............................................... 108 19.1 core buck swit ching regulator .......................108 19.2 3.3v ldo (ldo3p3) ........................................108 19.3 cldo ...............................................................109 19.4 lnldo .............................................................110 20. system power consumption ....................... 111 20.1 wlan current consumpti on ............................111 20.1.1 2.4 ghz mode ......................................111 20.2 bluetooth and fm current consumption ..........112 21. interface timing and ac characteristics ... 113 21.1 sdio default mode timing ..............................113 21.2 sdio high-speed mode timing .......................114 21.3 gspi signal timing ...........................................115 21.4 jtag timing ....................................................116 22. power-up sequence and timing................. 117 22.1 sequencing of reset and regulator control signals .................................................117 22.1.1 description of cont rol signals ..............117 22.1.2 control signal timing diagrams ...........117 23. package information .................................... 119 23.1 package thermal characteristics ....................119 23.1.1 junction temperature estimation and psi versus theta jc ......................................... 119 24. mechanical information.. .............................. 120 25. ordering information.................................... 126 document history page ............................................... 127 sales, solutions, and legal information .................... 128
document no. 002-14797 rev. *h page 7 of 128 cyw4343x 1. overview 1.1 overview the cypress cyw4343x provides the highest level of integration for a mobile or handheld wireless system, with integrated ieee 80 2.11 b/g/n. it provi des a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in siz e, form, and function. the cyw4343x is designed to address the needs of highly mobile devices that require minimal power consumption and reliable operation. figure 3 on page 7 figure 4 on page 8 figure 3 on page 7 shows the interconnection of all the major physical blo cks in the cyw4343x and their associated external inter- faces, which are described in great er detail in subsequent sections. figure 3. cyw4343x block diagram common ? and ? radio ? digital sw reg ldox2 lpo xtal ? osc. bpf wlan sdio gspi jtag* arm cm3 backplane bt \ wlan eci wdt otp gpio uart jtag * ram rom pmu control mac lnpphy radio btfm ? clock ? control sleep \ tim e ? keeping clock ? management pmu pmu ? ctrl por if pll bt ? phy modem digital ? demod. ? & ? bit ? sync digital mod. bpl buffer apu bt ? clock/ ? hopper lcu rx/tx buffer wimax ? coex ptu uart debug ? uart i 2 s/pcm gpio wake/ sleep ? ctrl i/o ? port ? control ahb ? bus ? matrix cortex m3 etm jtag* sdp ram rom patch interctrl dma bus ? arb ? arm ? ip wd ? timer sw ? timer gpio ctrl fm ? rx fm ? digital fm ? rf rssi lo gen. dpll lna fm ? demod. ? mdx ? rds ? decode control fm i/f apb fm_rx rf pa digital i/o sdio ? or ? gspi debug ieee ? 802.11a/b/g/n gpio uart 2.4 ? ghz 2.4 ? ghz pa shared ? lna power supply sleep ? clk xtal wimax ? coex. bluerf ? interface lpo xo ? buffer xtal vbat vregs bt_reg_on ahb ? to ? apb ? bridge ahb adc adc supported ? over ? sdio ? or ? bt ? pcm jtag ? supported ? over ? sdio ? or ? bt ? pcm * ? via ? gpio ? configuration, ? jtag ? is ? supported ? over ? sdio ? or ? bt ? pcm por wl_reg_on
document no. 002-14797 rev. *h page 8 of 128 cyw4343x figure 4. cyw4343x block diagram common ? and ? radio ? digital swreg ldox2 lpo xtal ? osc. bpf wlan sdio gspi jtag* arm cm3 backplane bt \ wlan eci wdt otp gpio uart jtag* ram rom pmu control mac lnpphy radio btfm ? clock ? control sleep \ time ? keeping clock ? management pmu pmu ? ctrl por if pll bt ? phy modem digital ? demod. ? & ? bit ? sync digital mod. bpl buffer apu bt ? clock/ ? hopper lcu rx/tx buffer wimax ? coex ptu uart debug ? uart pcm gpio wake/ sleep ? ctrl i/o ? port ? control ahb ? bus ? matrix cortex m3 etm jtag* sdp ram rom patch interctrl dma bus ? arb ? arm ? ip wd ? timer sw ? timer gpio ctrl fm ? rx fm ? digital fm ? rf rssi lo gen. dpll lna fm ? demod. ? mdx ? rds ? decode control fm i/f apb fm_rx rf pa digital i/o sdio ? or ? gspi debug ieee ? 802.11a/b/g/n gpio uart 2.4 ? ghz 2.4 ? ghz pa shared ? lna power supply sleep ? clk xtal wimax ? coex. bluerf ? interface lpo xo ? buffer xtal vbat vregs bt_reg_on ahb ? to ? apb ? bridge ahb adc adc supported ? over ? sdio ? or ? bt ? pcm jtag ? supported ? over ? sdio ? or ? bt ? pcm * ? via ? gpio ? configuration, ? jtag ? is ? supported ? over ? sdio ? or ? bt ? pcm por wl_reg_on
document no. 002-14797 rev. *h page 9 of 128 cyw4343x 1.2 features the cyw4343x supports the following wlan, bluetooth, and fm features: ieee 802.11b/g/n single-band radi o with an internal power amplifier, lna, and t/r switch bluetooth v4.1 with integrated class 1 pa concurrent bluetooth, fm (rx) rds/rbds, and wlan operation on-chip wlan driver execution capable of supporting ieee 802.11 functionality simultaneous bt/wlan reception with a single antenna wlan host interface options: ? sdio v2.0, including default and high-speed timing. ? gspi?up to a 50 mhz clock rate bt uart (up to 4 mbps) host digital interface that can be used concurrently with the above wlan host interfaces. eci?enhanced coexistence support, which coordina tes bt sco transmissions around wlan receptions. i 2 s/pcm for fm/bt audio, hci for fm block control hci high-speed uart (h4 and h5) transport support wideband speech support (16 bits, 16 khz sampling pcm, through i 2 s and pcm interfaces) bluetooth smartaudio ? technology improves voice and music quality to headsets. bluetooth low power inquiry and page scan bluetooth low energy (ble) support bluetooth packet loss concealment (plc) fm advanced internal antenna support fm auto searching/tuning functions fm multiple audio routing options: i 2 s, pcm, esco, and a2dp fm mono-stereo blending and switching, and soft mute support fm audio pause detection support multiple simultaneous a2dp audio streams fm over bluetooth operation and on-chip stereo headset emulation 1.3 standards compliance the cyw4343x supports the following standards: bluetooth 2.1 + edr bluetooth 3.0 bluetooth 4.1 (bluetooth low energy) 65 mhz to 108 mhz fm bands (us, europe, and japan) ieee 802.11n?handheld device class (section 11) ieee 802.11b ieee 802.11g ieee 802.11d ieee 802.11h ieee 802.11i the cyw4343x will support the follo wing future drafts/standards: ieee 802.11r ? fast r oaming (between aps) ieee 802.11k ? resource management ieee 802.11w ? secure management frames ieee 802.11 extensions: ieee 802.11e qos enhancem ents (as per the wmm ? specification is already supported) ieee 802.11i mac enhancements ieee 802.11r fast roaming support ieee 802.11k radio resource measurement
document no. 002-14797 rev. *h page 10 of 128 cyw4343x the cyw4343x supports the following securi ty features and proprietary protocols: security: ? wep ? wpa ? personal ? wpa2 ? personal ? wmm ? wmm-ps (u-apsd) ? wmm-sa ? wapi ? aes (hardware accelerator) ? tkip (host-computed) ? ckip (sw support) proprietary protocols: ? ccxv2 ? ccxv3 ? ccxv4 ? ccxv5 ieee 802.15.2 coexistence compliance ? on silicon solution compliant with ieee 3-wire requirements.
document no. 002-14797 rev. *h page 11 of 128 cyw4343x 2. power supplies and power management 2.1 power supply topology one buck regulator, multiple ldo regulators, and a power man agement unit (pmu) are integrated into the cyw4343x. all regula- tors are programmable via the pmu. these blocks simplify powe r supply design for bluetooth, wlan, and fm functions in embed- ded designs. a single vbat (3.0v to 4.8v dc maximum) and vddio supply (1.8 v to 3.3v) can be used, with all additional voltages being pro- vided by the regulators in the cyw4343x. two control signals, bt_reg_on and wl_r eg_on, are used to pow er up the regulators and take the respecti ve circuit blocks out of reset. the cbuck cldo and lnldo power up when any of the reset signals are deasserted. all regulators are powered down only when both bt_reg_on and wl_reg_on are deasserted. the cldo and lnldo can be turned on and off based on the dynamic demands of the digital baseband. the cyw4343x allows for an extremely low power-consumpti on mode by completely shutting down the cbuck, cldo, and lnldo regulators. when in this state, lp ldo1 provides the cyw4343x with all requ ired voltage, further re ducing leakage currents . note: vbat should be connected to the ldo_vddb at5v and sr_vddbat5v pins of the device. note: vddio should be connected to the sys_vddio and w cc_vddio pins wcc_vddio pin of the device. 2.2 cyw4343x pmu features the pmu supports the following: vbat to 1.35vout (170 ma nominal, 370 ma maxi mum) core-buck (cbuck) switching regulator vbat to 3.3vout (250 ma nominal, 450 ma maximum 800 ma peak maximum) ldo3p3 1.35v to 1.2vout (100 ma nominal, 150 ma maximum) lnldo 1.35v to 1.2vout (80 ma nominal, 200 ma maximum) cldo with bypass mode for deep sleep additional internal ldos (not externally accessible) pmu internal timer auto-calibration by the crystal clock fo r precise wake-up timing from extremely low power-consumption mode. pmu input supplies automatic sensing and fa st switching to support a4wp operations. figure 5 on page 12 figure 6 on page 13 figure 7 on page 14 and figure 8 on page 15figure 9 on page 16 figure 10 on page 17 show the typical power topology of the cyw4343x.
document no. 002-14797 rev. *h page 12 of 128 cyw4343x figure 5. typical power topology (1 of 2)(4343s) mini ? pmu vsel1 wl ? rf?logen wl ? rf?rx ? lna wl ? rf?adc ? ref wl ? rf?tx wl ? rf?afe ? and ? tia wl ? rf?xtal internal ? vcoldo 80 ? ma ? (nmos) internal ? rxldo 10 ? ma ? (nmos) internal ? adcldo 10 ? ma ? (nmos) internal ? txldo 80 ? ma ? (pmos) internal ? afeldo 80 ? ma ? (nmos) lnldo (100 ? ma) 1.2v 1.2v 1.2v 1.2v fm ? lna, ? mixer fm ? pll, ? logen, ? audio ? dac cl ? ldo peak: ? 200 ? ma avg: ? 80 ? ma (bypass ? in ? deep \ sleep) core ? buck ? regulator ? peak: ? 370 ? ma avg: ? 170 ? ma lpldo1 (5 ? ma) 2.2 ? uh 0603 1.35v 1 . 1 v 1.2v 1.2v sr_vddbat5v vdd1p35 ldo_vdd_1p5 4.7 ? uf 0402 sr_pvss sr_vlx wptldo (40 ? ma) 1.3v sys_vddio (40 ? ma) o_wpt_resetb o_wl_resetb wl_reg_on wpt_1p8 (40 ? ma) o_bt_resetb bt_reg_on wcc_vddio wcc_vddio (40 ? ma) pmu_vss gnd sr_vbat5v vbat int_sr_vbat cyw4343s_wpt 1.2v vbat: operational: 2.4?4.8v performance: 3.0?4.8v absolute ? maximum: 5.5v vddio operational: 1.8?3.3v sys_vddio wpt_1p8 600 ? @ 100 ? mhz 2.2 ? uf 0402 0.1 ? uf 0201 4.6 ? ma wlrf_xtal_ vdd1p2 wl ? rf?tx ? mixer ? and ? pa (not ? all ? versions) wl ? rf?rfpll ? pfd ? and ? mmd fm_rfvdd fm_rfpll 10 ? ma ? average, ? > ? 10 ? ma ? at ? start \ up vout_lnldo 2.2 ? uf 0402 vddc1 vddc2 (avs) vout_cldo 1.3v, ? 1.2v, ? or ? 0.95v wlan/bt/clb/top, ? always ? on wl ? otp wl ? digital ? and ? phy wl ? vddm ? (sroms ? & ? aos) bt ? vddm bt ? digital mini ? pmu ? is ? placed ? in ? wl ? radio vbat supply ? ball supply ? bump/pad ground ? ball ground ? bump/pad external ? to ? chip power ? switch no ? power ? switch no ? dedicated ? power ? switch, ? but ? internal ? power \ down ? modes ? and ? block \ specific ? power ? switches bt/wlan ? reset balls (320 ? ma) sw1
document no. 002-14797 rev. *h page 13 of 128 cyw4343x figure 6. typical power topology (1 of 2)(4343w+43cs4343w1) mini ? pmu vsel1 wl ? rf?logen wl ? rf?rx ? lna wl ? rf?adc ? ref wl ? rf?tx wl ? rf?afe ? and ? tia wl ? rf?xtal internal ? vcoldo 80 ? ma ? (nmos) internal ? rxldo 10 ? ma ? (nmos) internal ? adcldo 10 ? ma ? (nmos) internal ? txldo 80 ? ma ? (pmos) internal ? afeldo 80 ? ma ? (nmos) lnldo (100 ? ma) 1.2v 1.2v 1.2v 1.2v fm ? lna, ? mixer fm ? pll, ? logen, ? audio ? dac cl ? ldo peak: ? 200 ? ma avg: ? 80 ? ma (bypass ? in ? deep \ sleep) core ? buck ? regulator ? peak: ? 370 ? ma avg: ? 170 ? ma lpldo1 (5 ? ma) 2.2 ? uh 0603 1.35v 1 . 1 v 1.2v 1.2v sr_vddbat5v vdd1p35 ldo_vdd_1p5 4.7 ? uf 0402 sr_pvss sr_vlx wptldo (40 ? ma) 1.3v sys_vddio (40 ? ma) o_wpt_resetb o_wl_resetb wl_reg_on wpt_1p8 (40 ? ma) o_bt_resetb bt_reg_on wcc_vddio wcc_vddio (40 ? ma) pmu_vss gnd sr_vbat5v vbat int_sr_vbat 1.2v vbat: operational: 2.4?4.8v performance: 3.0?4.8v absolute ? maximum: 5.5v vddio operational: 1.8?3.3v sys_vddio wpt_1p8 600 ? @ 100 ? mhz 2.2 ? uf 0402 0.1 ? uf 0201 4.6 ? ma wlrf_xtal_ vdd1p2 wl ? rf?tx ? mixer ? and ? pa (not ? all ? versions) wl ? rf?rfpll ? pfd ? and ? mmd fm_rfvdd fm_rfpll 10 ? ma ? average, ? > ? 10 ? ma ? at ? start \ up vout_lnldo 2.2 ? uf 0402 vddc1 vddc2 (avs) vout_cldo 1.3v, ? 1.2v, ? or ? 0.95v wlan/bt/clb/top, ? always ? on wl ? otp wl ? digital ? and ? phy wl ? vddm ? (sroms ? & ? aos) bt ? vddm bt ? digital mini ? pmu ? is ? placed ? in ? wl ? radio vbat supply ? ball supply ? bump/pad ground ? ball ground ? bump/pad external ? to ? chip power ? switch no ? power ? switch no ? dedicated ? power ? switch, ? but ? internal ? power \ down ? modes ? and ? block \ specific ? power ? switches bt/wlan ? reset balls (320 ? ma) sw1 cyw4343x
document no. 002-14797 rev. *h page 14 of 128 cyw4343x figure 7. typical power topology (1 of 2) mini ? pmu wl ? rf?logen wl ? rf?rx ? lna wl ? rf?adc ? ref wl ? rf?tx wl ? rf?afe ? and ? tia internal ? vcoldo 80 ? ma ? (nmos) internal ? rxldo 10 ? ma ? (nmos) internal ? adcldo 10 ? ma ? (nmos) internal ? txldo 80 ? ma ? (pmos) internal ? afeldo 80 ? ma ? (nmos) lnldo (100 ? ma) 1.2v 1.2v 1.2v 1.2v cl ? ldo peak: ? 200 ? ma avg: ? 80 ? ma (bypass ? in ? deep \ sleep) core ? buck ? regulator ? peak: ? 370 ? ma avg: ? 170 ? ma lpldo1 (5 ? ma) 2.2 ? uh 0603 1.35v 1 . 1 v 1.2v 1.2v sr_vddbat5v vdd1p35 ldo_vdd_1p5 4.7 ? uf 0402 sr_pvss sr_vlx o_wl_resetb wl_reg_on o_bt_resetb bt_reg_on wcc_vddio wcc_vddio (40 ? ma) pmu_vss gnd sr_vbat5v vbat int_sr_vbat cyw4343x 1.2v vbat: operational: 2.4?4.8v performance: 3.0?4.8v absolute ? maximum: 5.5v vddio operational: 1.8?3.3v wl ? rf?tx ? mixer ? and ? pa (not ? all ? versions) vout_lnldo 2.2 ? uf 0402 vddc1 vddc2 (avs) vout_cldo 1.3v, ? 1.2v, ? or ? 0.95v wlan/bt/clb/top, ? always ? on wl ? otp wl ? digital ? and ? phy wl ? vddm ? (sroms ? & ? aos) bt ? vddm bt ? digital mini ? pmu ? is ? placed ? in ? wl ? radio vbat supply ? ball supply ? bump/pad ground ? ball ground ? bump/pad external ? to ? chip power ? switch no ? power ? switch no ? dedicated ? power ? switch, ? but ? internal ? power \ down ? modes ? and ? block \ specific ? power ? switches bt/wlan ? reset balls (320 ? ma) sw1 wl ? rf?xtal fm ? lna, ? mixer, ? tia, ? vco fm ? pll, ? logen, ? audio ? dac/bt ? pll 600 ? @ 100 ? mhz 2.2 ? uf 0402 0.1 ? uf 0201 4.6 ? ma wlrf_xtal_ vdd1p2 wl ? rf?rfpll ? pfd ? and ? mmd fm_rf_vdd btfm_pll_vdd 10 ? ma ? average, ? > ? 10 ? ma ? at ? start \ up bt ? lna, ? mixer, ? vco 6.4 ? ma bt ? adc, ? filter bt_vco_vdd bt_if_vdd
document no. 002-14797 rev. *h page 15 of 128 cyw4343x figure 8. typical power topology (2 of 2)(4343s) cyw4343s_wpt 1.8v, ? 2.5v, ? and ? 3.3v 1 ? uf 0201 4.7 ? uf 0402 ldo3p3 ? with back \ power ? protection (peak ? 450 \ 800 ? ma 200 ? ma ? average) vout_3p3 3.3v ldo_ vddbat5v wpt_3p3 vbat wlrf_pa_vdd sw2 peak: ? 92 ? ma average: ? 75 ? ma resistance: ? 1 ? ohm bt_pavdd 2.5v ? cap \ less ? lnldo (10 ? ma) wl ? rf?pa ? (2.4 ? ghz) wl ? otp ? 3.3v wl ? rf?adc, ? afe, ? logen, ? lna, ? nmos ? mini \ pmu ? ldos bt ? class ? 1 ? pa peak: ? 70 ? ma average: ? 15 ? ma 6.4 ? ma 480 ? to ? 800 ? ma supply ? ball external ? to ? chip power ? switch no ? power ? switch no ? dedicated ? power ? switch, ? but ? internal ? power \ down ? modes ? and ? block \ specific ? power ? switches placed ? inside ? wl ? radio 1 ? uf 0201 22 ? ohm wl ? bbpll/dfll 6.4 ? ma
document no. 002-14797 rev. *h page 16 of 128 cyw4343x figure 9. typical power topology (2 of 2)(4343w+43cs4343w1) 1.8v, ? 2.5v, ? and ? 3.3v 1 ? uf 0201 4.7 ? uf 0402 ldo3p3 ? with back \ power ? protection (peak ? 450 \ 800 ? ma 200 ? ma ? average) vout_3p3 3.3v ldo_ vddbat5v wpt_3p3 vbat wlrf_pa_vdd sw2 peak: ? 92 ? ma average: ? 75 ? ma resistance: ? 1 ? ohm bt_pavdd 2.5v ? cap \ less ? lnldo (10 ? ma) wl ? rf?pa ? (2.4 ? ghz) wl ? otp ? 3.3v wl ? rf?adc, ? afe, ? logen, ? lna, ? nmos ? mini \ pmu ? ldos bt ? class ? 1 ? pa peak: ? 70 ? ma average: ? 15 ? ma 6.4 ? ma 480 ? to ? 800 ? ma supply ? ball external ? to ? chip power ? switch no ? power ? switch no ? dedicated ? power ? switch, ? but ? internal ? power \ down ? modes ? and ? block \ specific ? power ? switches placed ? inside ? wl ? radio 1 ? uf 0201 22 ? ohm wl ? bbpll/dfll 6.4 ? ma cyw4343x
document no. 002-14797 rev. *h page 17 of 128 cyw4343x figure 10. typical power topology (2 of 2) cyw4343x 1.8v, ? 2.5v, ? and ? 3.3v 1 ? uf 0201 4.7 ? uf 0402 ldo3p3 ? with back \ power ? protection (peak ? 450 \ 800 ? ma 200 ? ma ? average) vout_3p3 3.3v ldo_ vddbat5v vbat wlrf_pa_vdd bt_pavdd 2.5v ? cap \ less ? lnldo (10 ? ma) wl ? rf?pa ? (2.4 ? ghz) wl ? otp ? 3.3v wl ? rf?adc, ? afe, ? logen, ? lna, ? nmos ? mini \ pmu ? ldos bt ? class ? 1 ? pa peak: ? 70 ? ma average: ? 15 ? ma 6.4 ? ma 480 ? to ? 800 ? ma supply ? ball external ? to ? chip power ? switch no ? power ? switch no ? dedicated ? power ? switch, ? but ? internal ? power \ down ? modes ? and ? block \ specific ? power ? switches placed ? inside ? wl ? radio 1 ? uf 0201 22 ? ohm wl ? bbpll/dfll 6.4 ? ma
document no. 002-14797 rev. *h page 18 of 128 cyw4343x 2.3 wlan power management the cyw4343x has been designed with the string ent power consumption requirements of mo bile devices in mind. all areas of the chip design are optimized to minimize power consumption. silic on processes and cell libraries were chosen to reduce leakage cur - rent and supply voltages. additionally, the cyw4343x integrated ram is a high volatile memory with dynamic clock control. the dominant supply current consumed by the ram is leakage current only. additionally, the cyw4343x includes an advanced wlan power management unit (pmu) sequencer. the pmu sequencer prov ides significant power savings by putting the cyw4343x into various power management states appropriate to the operating environment and the activities that are being performed. the power management unit enables and disables internal regulators, swit ches, and other blocks based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. power-u p sequences are fully programmable. configurable, free-running counters (running at the 32. 768 khz lpo clock) in the pmu sequencer are used to turn on/turn off individual regulators a nd power switches. clock speeds are dynamically changed (or gated altogether) for the current mode. slower cl ock speeds are used wherever possible. the cyw4343x wlan power states are described as follows: active mode? all wlan blocks in the cy w4343x are powered up a nd fully functional with active carr ier sensing and frame transmission and receiving. all requ ired regulators are enabled and put in t he most efficient mode based on the load current. clock speeds are dynamically adjusted by the pmu sequencer. doze mode?the radio, analog domains, and most of the linea r regulators are powered down. the rest of the cyw4343x remains powered up in an idle state. all main clocks (pll, cr ystal oscillator) are shut down to reduce active power to the minimum. the 32.768 khz lpo clock is available only for th e pmu sequencer. this condition is necessary to allow the pmu sequencer to wake up the chip and transition to active mode. in doze mode, the primary power consumed is due to leakage current. deep-sleep mode?most of the chip, including analog and digital domains, and most of the regulators are powered off. logic states in the digital core are saved and preserved to re tention memory in the always-on domain before the digital core is powered off. to avoid lengthy hardware reinitialization, the logic states in the digital core are restored to their pre-deep - sleep settings when a wake-up event is triggered by an external interrupt, a host resume through the sdio bus, or by the pmu timers. power-down mode?the cyw4343x is effectively powered off by sh utting down all internal regulators. the chip is brought out of this mode by external logi c re-enabling the internal regulators. 2.4 pmu sequencing the pmu sequencer is used to minimize syst em power consumption. it ena bles and disables various s ystem resources based on a computation of required resources and a tabl e that describes the relationship between re sources and the time required to enable and disable them. resource requests can derive from several sources: clo ck requests from cores, the minimum resources defined in the resourcemin register, and the resources requested by any active resource re quest timers. the pmu sequencer maps clock requests into a set o f resources required to pro duce the requested clocks. each resource is in one of the following four states: enabled disabled transition_on transition_off the timer value is 0 when the resource is enabled or disabled and nonzero during state transitio n. the timer is loaded with the time_on or time_off value of the resource when the pmu determines that the resource must be e nabled or disabled. that timer dec - rements on each 32.768 khz pmu clock. when it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. if the time_on value is 0, the resource can transition i mmediately from disabled to enabled. similarly, a time_off val ue of 0 indicates that the resource can transition imm ediately from enabled to disabled. the terms enable sequence and disable sequence refer to either the immediate transition or the timer load-decrement sequence. during each clock cycle, t he pmu sequencer performs the following actions: computes the required resource set based on requests and the resource dependency table. decrements all timers whose values are nonzero. if a timer reaches 0, the pmu clears the resourcepending bit for the resource and inverts the resourcestate bit. compares the request with the current resource status and determines which re sources must be enabled or disabled. initiates a disable sequence for each re source that is enabled, no longer being requested, and has no powered-up depen- dents.
document no. 002-14797 rev. *h page 19 of 128 cyw4343x initiates an enable sequence for each resource that is disa bled, is being requested, and has all of its dependencies enabled. 2.5 power-off shutdown the cyw4343x provides a low-power shutdown feature that allows the device to be tu rned off while the host, and any other device s in the system, remain operational. when th e cyw4343x is not needed in the system, vddio_rf and vddc are shut down while vddio remains powered. this allows the cyw4343x to be effectiv ely off while keeping the i/o pins powered so that they do not draw extra current from any other devices connected to the i/o. during a low-power shutdown state, provided vddio remains applied to the cyw4343x, all outputs are tristated, and most input signals are disabled. input voltages must remain within the limits defined for normal operation. this is done to prevent curren t paths or create loading on any digital signals in the system, and enabl es the cyw4343x to be fully integrated in an embedded device a nd to take full advantage of the lowest power-savings modes. when the cyw4343x is powered on from this state, it is the same as a normal power- up, and the device does not retain any infor- mation about its state from before it was powered down. 2.6 power-up/power-down/reset circuits the cyw4343x has two signals (see table 2 ) that enable or disable the bluetooth and wlan circuits and the internal regulator blocks, allowing the host to control power consumption. for timing diagrams of these signals and the re quired power-up sequence s, see section 22.: ?power-up sequence and timing,? on page 116 . 2.7 wireless charging the cyw4343x, when paired with a broadcom bcm5935x wireless power transfer (wpt) front-end device, complies with the fol- lowing three wireless charging standards: alliance for wireless power (a4wp) wireless power consortium (wpc) power matters alliance (pma) to support the wpc and pma standards, control-plane signaling is accomplished using in-band signaling between the bcm5935x wpt front-end device (located in the power receiv ing entity) and the power transmitting wireless charger. to support the a4wp standard, e nergy is transferred from a power transmitting unit (ptu) to a power receiving unit (pru). the energy transferred charges the pru battery. bidirectional commu nication between the ptu and pru is accomplished using blue- tooth low energy (ble), where the ptu is a ble client and the pru is a ble server. using a ble link, the pru sends performance data to the ptu so that it can adapt its power output to meet the needs of the pru. the most common use for wireless charging is to charge a mobile device battery. figure 11 shows a simple block diagram of a syst em that supports the a4wp standard. table 2. power-up/power-down/reset control signals signal description wl_reg_on this signal is used by the pmu (with bt_reg_on) to power-up t he wlan section. it is also or-gated with the bt_reg_on input to control the internal cyw4343x regula tors. when this pin is high, the regulators are enabled and the wlan section is out of reset. when this pin is low, the wlan section is in reset. if bt_reg_on and wl_reg_on are both low, the regulators are disabled. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. bt_reg_on this signal is used by the pm u (with wl_reg_on) to decide whether or not to power down the internal cyw4343x regulators. if bt_reg_on and wl_reg_on are low, the regula tors will be disabled. this pin has an internal 200 k ? pull-down resistor that is enabled by def ault. it can be disabled through programming.
document no. 002-14797 rev. *h page 20 of 128 cyw4343x figure 11. a4wp system block diagram note: a single ptu can be used to charge multiple devices. figure 12 shows an example of the magnetic coupling between a single ptu and one or more prus. figure 12. magnetic coupling for wireless charging figure 13 shows an example a4wp-compliant wireless charging implementation. power ? transmitting ? unit (ptu) aka ? power ? plate ble ? client power ? receiving ? unit (pru) a4wp \ compatible ? mobile ? device ble ? server wireless ? power ? transfer ? at ? 6.78 ? mhz bt bluetooth ? low \ energy ? (ble) ? bidirectional ? communication ? enables ? the ? transmitter ? to ? adapt ? to ? mobile ? device ? system ? needs. bt tx rx1 rx2 rx3 power ? transmitting ? unit power ? receiving ? unit(s)
document no. 002-14797 rev. *h page 21 of 128 cyw4343x figure 13. an example multimode wireless charging implementation figure 14 shows the signal interface between a cyw4343x and a cyw59350. figure 14. cyw4343x interface to a bcm59350 motherboard bt_vddio ? domain wake \ up external ? charger wpt ? front ? end ? (power ? ic) bridge ? rectifier voltage ? regulator load control bsc ? if slave power ? monitoring/ control wpt_irq ntc battery ? charging usb pmu vddio vbat host ? (ap) bsc bsc bt_reg_on 3.3v ldo wpt_irq bsc_clk bsc_sda nfc_gpio nfc ? ic otp ? for ? a4wpt ? parameters bcm5935x 1.8v ldo wpc/pma coil a4wp coil vbat spdt 1v8 spdt wpt_3v3 ? (vbat) wpt_1v8 ? (vddio) ldo_vddbat5v, sr_vddbat5v sys_vddio, wcc_vddio pmu por internal power vbat v1p8sys wl_reg_on cyw4343x bcm59350 ? wireless ? charging ? pmu bt_gpio_3 ? (wpt_intb) bt_gpio_5 ? (bsc_scl) bt_gpio_4 ? (bsc_sda) cyw4343x
document no. 002-14797 rev. *h page 22 of 128 cyw4343x 3. frequency references an external crystal is used for generatin g all radio frequencies and normal operation clocking. as an alternative, an external fre- quency reference driven by a temperature-compensated crystal o scillator (tcxo) signal may be used. no software settings are required to differentiate between the two. in addition, a low- power oscillator (lpo) is provided for lower power mode timing. 3.1 crystal interface and clock generation the cyw4343x can use an external crystal to provide a frequency reference. the recommended configuration for the crystal oscil- lator, including all external components, is shown in figure 15 . consult the reference schemati cs for the latest configuration. figure 15. recommended oscillator configuration the cyw4343x uses a fractional-n synthesiz er to generate the radio frequencies, clo cks, and data/packet timing so that it can operate using numerous frequency references. the frequency reference can be an external source such as a tcxo or a crystal interfaced directly to the cyw4343x. the default frequency reference setting is a 37.4 mhz crystal or tcxo. the signal requirements and characteristics for the crys tal interface are shown in table 3 on page 23 . note: although the fractional-n synthesizer can support many refe rence frequencies, frequencies other than the default require support to be added in the driver, plus additional ext ensive system testing. contact broadcom for further details. 3.2 tcxo as an alternative to a crystal, an external precision tcxo can be used as the frequency reference, provided that it meets the p hase noise requirements listed in table 3 on page 23 . if the tcxo is dedicated to driv ing the cyw4343x, it should be connected to th e wlrf_xtal_xop pin through an external capac- itor with value ranges from 200 pf to 1000 pf as shown in figure 16 . 12 ? 27 pf 12 ? 27 pf wlrf_xtal_xon wlrf_xtal_xop c c r note : resistor value determined by crystal drive level. see reference schematics for details.
document no. 002-14797 rev. *h page 23 of 128 cyw4343x figure 16. recommended circuit to use with an external dedicated tcxo 3.3 external 32.768 khz low-power oscillator the cyw4343x uses a secondary low-frequency sleep clock for low-pow er mode timing. either the internal low-precision lpo or an external 32.768 khz precision oscillator is required. the internal lpo frequency range is approximately 33 khz 30% over proce ss, voltage, and temperature, which is adequate for some applications . however, one trade-off caused by this wide lpo tolerance is a small current consumption increase during power save mode that is incurred by the need to wake up earlier to avoid missing bea- cons. table 3. crystal o scillator and external clock requirements and performance parameter conditions/notes crystal external frequency reference min. typ. max. min. typ. max. units frequency ? ? 37.4 a a. the frequency step size is approximately 80 hz. the cyw4343x does not auto-detect the reference clock frequency; the frequenc y is specified in the software and/or nvram file. ???? mhz crystal load capacitance ? ? 12 ? ? ? ? pf esr ? ? ? 60 ? ? ? ? drive level external crystal must be able to tolerate this drive level. 200 ? ? ? ? ? w input impedance (wlrf_xtal_xop) resistive ? ? ? 10k 100k ? ? capacitive ? ? ? ? ? 7 pf wlrf_xtal_xop input voltage ac-coupled analog signal ? ? ? 400 b b. to use 256-qam, a 800 mv minimum voltage is required. ?1260 mv p-p wlrf_xtal_xop input low level dc-coupled digital signal ? ? ? 0 ? 0.2 v wlrf_xtal_xop input high level dc-coupled digital signal ? ? ? 1.0 ? 1.26 v frequency tolerance initial + over temperature ? ?20 ? 20 ?20 ? 20 ppm duty cycle 37.4 mhz clock ? ? ? 40 50 60 % phase noise c, d, e (ieee 802.11 b/g) c. for a clock reference other than 37.4 mhz, 20 log10(f/37.4 ) db should be added to the limits, where f = the reference clock frequency in mhz. d. phase noise is assumed flat above 100 khz. e. the cyw4343x supports a 26 mhz reference clock sharing option. see the phase noise requirement in the table. 37.4 mhz clock at 10 khz offset ? ? ? ? ? ?129 dbc/hz 37.4 mhz clock at 100 khz offset ? ? ? ? ? ?136 dbc/hz phase noise c, d, e (ieee 802.11n, 2.4 ghz) 37.4 mhz clock at 10 khz offset ? ? ? ? ? ?134 dbc/hz 37.4 mhz clock at 100 khz offset ? ? ? ? ? ?141 dbc/hz phase noise c, d, e (256-qam) 37.4 mhz clock at 10 khz offset ? ? ? ? ? ?140 dbc/hz 37.4 mhz clock at 100 khz offset ? ? ? ? ? ?147 dbc/hz tcxo nc 200 pf ? 1000 pf wlrf_xtal_xop wlrf_xtal_xon
document no. 002-14797 rev. *h page 24 of 128 cyw4343x whenever possible, the preferred approach is to use a precisio n external 32.768 khz clock that meets the requirements listed in table 4 on page 24 . note: the cyw4343x will auto-detect the lpo clock. if it senses a clock on the ext_sleep_cl k pin, it will use that clock. if it doesn't sense a clock, it will use its own internal lpo. to use the internal lpo: tie ext_sleep_clk to ground. do not leave this pin floating. to use an external lpo: connect the external 32.768 khz clock to ext_sleep_clk. table 4. external 32.768 khz sleep-clock specifications parameter lpo clock units nominal input frequency 32.768 khz frequency accuracy 200 ppm duty cycle 30?70 % input signal amplitude 200?3300 mv, p-p signal type square wave or sine wave ? input impedance a a. when power is applied or switched off. >100 k ? <5 pf clock jitter <10,000 ppm
document no. 002-14797 rev. *h page 25 of 128 cyw4343x 4. wlan system interfaces 4.1 sdio v2.0 the cyw4343x wlan section supports sdio ve rsion 2.0. for both 1-bit (25 mbps) and 4- bit modes (100 mbps), as well as high speed 4-bit mode (50 mhz clocks?200 mbps). it has the ability to map the interrupt signal on a gp io pin. this out-of-band inter rupt signal notifies the host when the wlan device wants to turn on the sdio interface. the ability to force control of the gated cl ocks from within the wlan chip is also provided. sdio mode is enabled using the strapping option pins. see table 24 on page 86 for details. three functions are supported: function 0 standard sdio function. the maximum block size is 32 bytes. function 1 backplane function to access the internal syste m-on-a-chip (soc) address space. the maximum block size is 64 bytes. function 2 wlan function for efficient wlan packet trans fer through dma. the maximum block size is 512 bytes. 4.1.1 sdio pin descriptions figure 17. signal connections to sdio host (sd 4-bit mode) figure 18. signal connections to sdio host (sd 1-bit mode) table 5. sdio pin descriptions sd 4-bit mode sd 1-bit mode gspi mode data0 data line 0 data data line do data output data1 data line 1 or interrupt irq interrupt irq interrupt data2 data line 2 nc not used nc not used data3 data line 3 nc not used cs card select clk clock clk clock sclk clock cmd command line cmd command line di data input sd ? host cmd dat[3:0] clk cyw4343x sd ? host cmd clk data irq cyw4343x
document no. 002-14797 rev. *h page 26 of 128 cyw4343x 4.2 generic spi mode in addition to the full sdio mode, the cyw4343x includes the option of using the simplified ge neric spi (gspi) interface/protoc ol. characteristics of the gspi mode include: up to 50 mhz operation fixed delays for responses and data from the device alignment to host gspi frames (16 or 32 bits) up to 2 kb frame size per transfer little-endian and big-endian configurations a configurable active edge for shifting packet transfer through dma for wlan gspi mode is enabled using the strapping option pins. see table 24 on page 86 for details. figure 19. signal connections to sdio host (gspi mode) 4.3 spi protocol the spi protocol supports both 16-bit and 32-bit word operation. byte endianess is supported in both modes. figure 20 and figure 21 on page 27 show the basic write and write/read commands. sd ? host di sclk do irq cs cyw4343x
document no. 002-14797 rev. *h page 27 of 128 cyw4343x figure 20. gspi write protocol figure 21. gspi read protocol
document no. 002-14797 rev. *h page 28 of 128 cyw4343x 4.3.1 command structure the gspi command structure is 32 bits. the bit positions and definitions are shown in figure 22 . figure 22. gspi command structure 4.3.1.1 write the host puts the first bit of the data onto the bus half a clock- cycle before the first active edge following the cs going low . the fol- lowing bits are clocked out on the falling edge of the gspi clock. the device samples the data on the active edge. 4.3.1.2 write/read the host reads on the rising edge of the cl ock requiring data from the device to be made available before the first rising-cloc k edge of the data. the last clock edge of the fi xed delay word can be used to represent the first bit of the following data word. thi s allows data to be ready for the first clock edge without relying on asynchronous delays. 4.3.1.3 read the read command always follows a separate write to set up the wl an device for a read. this comma nd differs from the write/read command in the following respects: a) chip selects go high between the command/address and the data, and b) the time interval between the command/address is not fixed. 4.3.2 status the gspi interface supports status notifica tion to the host after a read/write transaction. this status notification provides i nformation about packet errors, protocol errors, available packets in the rx queue, etc. the status informat ion helps reduce the number of inter- rupts to the host. the status-reporting feature can be switched off using a register bit, witho ut any timing overhead. the gspi bus timing for read/write transactions with and without status notification are as shown in figure 23 below and figure 24 on page 30 . see table 6 on page 30 for information on status-field details. 0 10 27 11 packet length - 11bits * address C 17 bits f1 f0 c a function no: 00 C func 0 01 C func 1 10 C func 2 11 C func 3 command : 0 C read 1 C write bcm_spid command structure 28 29 30 31 access : 0 C fixed address 1 C incremental address * 11h0 = 2048 bytes 0 10 27 11 packet length - 11bits * address C 17 bits f1 f0 c a function no: 00 C func 0: all spi-specific registers 01 C func 1: registers and memories belonging to other blocks in the chip (64 bytes max) 10 C func 2: dma channel 1. wlan packets up to 2048 bytes. 11 C func 3: dma channel 2 (optional). packets up to 2048 bytes. command : 0 C read 1 C write bcm_spid command structure 28 29 30 31 access : 0 C fixed address 1 C incremental address * 11h0 = 2048 bytes
document no. 002-14797 rev. *h page 29 of 128 cyw4343x figure 23. gspi signal timing without status c31 c30 c1 c0 d31 d30 d1 d0 command 32 bits write data 16*n bits sclk mosi c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits response delay c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits miso response delay d1 c31 c30 c1 c0 d31 d30 d1 d0 command 32 bits write data 16*n bits cs c31 c30 c1 c0 d31 d30 d1 d0 c31 c30 c1 c0 d31 d30 d1 d0 command 32 bits write data 16*n bits c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits response delay c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits response delay c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits response delay d1 c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits response delay d1 write write-read read cs sclk mosi miso cs sclk mosi
document no. 002-14797 rev. *h page 30 of 128 cyw4343x figure 24. gspi signal timing with status (response delay = 0) 4.4 gspi host-device handshake to initiate communication through the gspi after power-up, the ho st needs to bring up the wlan chip by writing to the wake-up wlan register bit. writing a 1 to this bit will start up the ne cessary crystals and plls so that the cyw4343x is ready for data trans- fer. the device can signal an interrupt to the host indicating that the device is awake and ready. this procedure also needs to be fol- lowed for waking up the device in sleep mode. the device can in terrupt the host using the wlan irq line whenever it has any information to pass to the host. on getting an interrupt, the host needs to read the interrupt and/or status register to determ ine the cause of the interrupt and then take necessary actions. table 6. gspi status field details bit name description 0 data not available the requested read data is not available. 1 underflow fifo underflow occurred due to current (f2, f3) read command. 2 overflow fifo overflow occurred due to current (f1, f2, f3) write command. 3 f2 interrupt f2 channel interrupt. 5 f2 rx ready f2 fifo is ready to receive data (fifo empty). 7 reserved ? 8 f2 packet available packet is av ailable/ready in f2 tx fifo. 9:19 f2 packet length length of packet available in f2 fifo c31 c0 d31 d1 d0 read data 16*n bits s0 s31 status 32 bits c31 c0 d31 d1 d0 command 32 bits read data 16*n bits s0 s31 status 32 bits c31 s0 c1 c0 d31 s31 d1 d0 command 32 bits write data 16*n bits s1 status 32 bits c31 c0 d31 d1 d0 s0 s31 c31 c0 d31 d1 d0 s0 s31 c31 c0 d31 d1 d0 s0 s31 c31 c0 d31 d1 d0 s0 s31 c31 s0 c1 c0 d31 s31 d1 d0 s1 c31 s0 c1 c0 d31 s31 d1 d0 s1 command 32 bits write write-read read miso cs sclk mosi miso cs sclk mosi miso cs sclk mosi
document no. 002-14797 rev. *h page 31 of 128 cyw4343x 4.4.1 boot-up sequence after power-up, the gspi host needs to wait 50 ms for the device to be out of reset. for this, the host needs to poll with a re ad com- mand to f0 address 0x14. address 0x14 contains a predefined bi t pattern. as soon as the host gets a response back with the corr ect register content, it implies that the device has powered up and is out of reset. after that, the host needs to set the wake-up wlan bit (f0 reg 0x00 bit 7). wake-up wlan turns the pll on; however, the pll doesn't lock until the host programs the pll registers to set the crystal frequency. for the first time after power-up, the host needs to wait for t he availability of the low-power clock inside the device. once i t is avail- able, the host needs to write to a pmu register to set the cryst al frequency. this will turn on the pll. after the pll is locke d, the chi- pactive interrupt is issued to the host. th is indicates device awake/ready status. see ta b l e 7 for information on gspi registers. in table 7 , the following notation is used for register access: r: readable from host and cpu w: writable from host u: writable from cpu table 7. gspi registers address register bit access default description x0000 word length 0 r/w/u 0 0: 16-bit word length 1: 32-bit word length endianess 1 r/w/u 0 0: little endian 1: big endian high-speed mode 4 r/w/u 1 0: normal mode. sa mple on spiclk rising edge, output on falling edge. 1: high-speed mode. sample and output on rising edge of spiclk (default). interrupt polarity 5 r/w/u 1 0: interrupt active polarity is low. 1: interrupt active polarity is high (default). wake-up 7 r/w 0 a write of 1 denotes a wake-up command from host to device. this will be followed by an f2 interrupt from the gspi device to host, indicating device awake status. x0002 status enable 0 r/w 1 0: no status sent to host after a read/write. 1: status sent to host after a read/write. interrupt with status 1 r/w 0 0: do not interrupt if status is sent. 1: interrupt host even if status is sent. x0003 reserved ? ? ? ? x0004 interrupt register 0 r/w 0 requested data not av ailable. cleared by writing a 1 to this location. 1 r 0 f2/f3 fifo underflow from the last read. 2 r 0 f2/f3 fifo overflow from the last write. 5 r 0 f2 packet available 6 r 0 f3 packet available 7 r 0 f1 overflow from the last write. x0005 interrupt register 5 r 0 f1 interrupt 6 r 0 f2 interrupt 7 r 0 f3 interrupt x0006, x0007 interrupt enable register 15:0 r/w/u 16'he0e7 particular interrupt is enabled if a corresponding bit is set. x0008 to x000b status register 31:0 r 32'h0000 same as status bit definitions x000c, x000d f1 info. register 0 r 1 f1 enabled 1 r 0 f1 ready for data transfer 13:2 r/u 12'h40 f1 maximum packet size
document no. 002-14797 rev. *h page 32 of 128 cyw4343x figure 25 on page 33 shows the wlan boot-up sequence from power-up to firmware download, including the initial device power- on reset (por) evoked by the wl_reg_on signal. after initial power-up, the wl_reg_on signal can be held low to disable the cyw4343x or pulsed low to induce a subsequent reset. note: the cyw4343x has an internal power-on reset (por) circuit. t he device will be held in reset for a maximum of 3 ms after vddc and vddio have both passed the 0.6v threshold. x000e, x000f f2 info. register 0 r/u 1 f2 enabled 1 r 0 f2 ready for data transfer 15:2 r/u 14'h800 f2 maximum packet size x0014 to x0017 test-read only register 31:0 r 32'hfeedbea d this register contains a prede fined pattern, which the host can read to determine if the gspi interface is working properly. x0018 to x001b test?r/w register 31:0 r/w/u 32'h00000000 this is a du mmy register where the host can write some pattern and read it back to determine if the gspi interface is working properly. x001c to x001f response delay registers 7:0 r/w 0x1d = 4, other registers = 0 individual response delays for f0, f1, f2, and f3. the value of the registers is the number of byte delays that are introduced before data is shifted out of the gspi interface during host reads. table 7. gspi registers (cont.) address register bit access default description
document no. 002-14797 rev. *h page 33 of 128 cyw4343x figure 25. wlan boot-up sequence < ? 1.5 ? ms after ? 15 ? ms 1 the ? reference ? clock ? is ? assumed ? to ? be ? up. ?? access ? to ? pll ? registers ? is ? possible. 15 ? 1 ms ? < ? 50 ? ms ? < ? 3 ? ms ? after ? a ? fixed ? delay ? following ? internal ? por ? going ? high, ? the ? device ? responds ? to ? host ? f0 ? (address ? 0x14) ? reads. vddio wl_reg_on vddc (from ? internal ? pmu) internal ? por device ? requests ? a ? reference ? clock. spi ? host ? interaction: host ? polls ? f0 ? (address ? 0x14) ? until ? it ? reads ? a ? predefined ? pattern. host ? sets ? wake \ up \ wlan ? bit ? and ? waits ? 15 ? ms 1 , ? the ? maximum ? time ? for ? reference ? clock ? availability. after ? 15 ? 1 ms, ? the ? host ? programs ? the ? pll ? registers ? to ? set ? the ? crystal ? frequency. host ? downloads ? code. chip \ active ? interrupt ? is ? asserted ? after ? the ? pll ? locks. vbat ramp ? time ? from ? 0v ? to ? 4.3v ? > ? 40 ? s 0.6v > ? 2 ? sleep ? clock ? cycles wl_irq 1 ? this ? wait ? time ? is ? programmable ? in ? sleep \ clock ? increments ? from ? 1 ? to ? 255 ? (30 ? us ? to ? 15 ? ms).
document no. 002-14797 rev. *h page 34 of 128 cyw4343x 5. wireless lan mac and phy 5.1 mac features the cyw4343x wlan mac supports features specified in the ieee 802.11 base st andard, and amended by ieee 802.11n. the salient features are listed below: transmission and reception of aggregated mpdus (a-mpdu). support for power management schemes, including wmm pow er-save, power-save multipoll (psmp) and multiphase psmp operation. support for immediate ack and block-ack policies. interframe space timing support, including rifs. support for rts/cts and cts-to-self frame sequences for protecting frame exchanges. back-off counters in hardware for supporting multiple priorities as specified in the wmm specification. timing synchronization function (tsf), network allocation ve ctor (nav) maintenance, and ta rget beacon transmission time (tbtt) generation in hardware. hardware off-load for aes-ccmp, legacy wpa tkip, legacy wep ciphers, wapi, and support for key management. support for coexistence with blueto oth and other external radios. programmable independent basic service set (ibss) or infrastructure basic service set functionality statistics counters for mib support. 5.1.1 mac description the cyw4343x wlan mac is designed to support high throughput operation with low-power consumpt ion. it does so without com- promising on bluetooth coexistence policies, thereby enabling optimal performance over both networks. in addition, several powe r- saving modes that have been implemented allow the mac to consum e very little power while maintaining network-wide timing syn- chronization. the architecture diagram of the mac is shown in figure 26 on page 34 . figure 26. wlan mac architecture embedded ? cpu ? interface host ? registers, ? dma ? engines tx \ fifo 32 ? kb wep wep, ? tkip, ? aes txe tx ? a \ mpdu rxe pmq psm shared ? memory 6 ? kb psm ucode memory ext \ ihr ifs backoff, ? btcx tsf nav ihr ? bus shm ? bus mac \ phy ? interface rx \ fifo 10 ? kb rx ? a \ mpdu
document no. 002-14797 rev. *h page 35 of 128 cyw4343x the following sections provide an overview of the important modules in the mac. 5.1.1.1 psm the programmable state machine (psm) is a microcoded engine that provides most of the low-level control to the hardware to impl e- ment the ieee 802.11 specificatio n. it is a microcontroller that is highly op timized for flow-control operations, which are pred ominant in implementations of communica tion protocols. the instruction set and fundam ental operations are simple and general, which allows algorithms to be optimized until very late in the design process. it also allows for changes to the algorithms to track evolving ieee 802.11 specifications. the psm fetches instructions from the microc ode memory. it uses the shared memory to obtain operands for instructions, as a dat a store, and to exchange data between both the host and the mac data pipeline (via the shm bus). the psm also uses a scratch-pad memory (similar to a register bank) to stor e frequently accessed and temporary variables. the psm exercises fine-grained control over the hardware engines by programming inte rnal hardware registers (ihr). these ihrs are collocated with the hardware functions they control and are accessed by the psm via the ihr bus. the psm fetches instructions from the microcode memory using an address determined by the progra m counter, an instruction lit- eral, or a program stack. for alu operations, the operands are obtained from shared memory, scratch-pad memory, ihrs, or instruction literals, and the results are written into the shared memo ry, scratch-pad memory, or ihrs. there are two basic branch instructions: conditional branches a nd alu-based branches. to better support the many decision point s in the ieee 802.11 algorithms, branches can depend on either r eadily available signals from the hardware modules (branch condi- tion signals are available to the psm without pollin g the ihrs) or on the results of alu operations. 5.1.1.2 wep the wired equivalent privacy (wep) engine encapsulates all the ha rdware accelerators to perform the encryption and decryption, as well as the mic computation and verification. the accelerators implement the following cipher algorithms: legacy wep, wpa tkip, and wpa2 aes-ccmp. based on the frame type and association in formation, the psm determines the appropriat e cipher algorithm to be used. it supplie s the keys to the hardware engines from an on-chip key table. the wep interfaces with the transmit engine (txe) to encrypt and co m- pute the mic on transmit frames and the re ceive engine (rxe) to decrypt and verify th e mic on receive frames. wapi is also sup- ported. 5.1.1.3 txe the transmit engine (txe) constitutes the transmit data path of the mac. it coordinates the dma engines to store the transmit frames in the txfifo. it interfaces with wep module to encrypt frames and transfers the frames across the mac-phy interface at the appropriate time determined by the channel access mechanisms. the data received from the dma engines are stored in transmit fi fos. the mac supports multiple logical queues to support traffi c streams that have different qos priority requirements. the psm uses the channel access information from the ifs module to sched - ule a queue from which the next frame is tr ansmitted. once the frame is scheduled, the txe hardware transmits the frame based o n a precise timing trigger received from the ifs module. the txe module also contains the hardware that allows the rapi d assembly of mpdus into an a-mpdu for transmission. the hard- ware module aggregates the encrypted mpdus by ad ding appropriate headers and pad delimiters as needed. 5.1.1.4 rxe the receive engine (rxe) constitutes the rece ive data path of the mac. it interfaces with the dma en gine to drain the received frames from the rx fifo. it transfers by tes across the mac-phy interface and interfac es with the wep module to decrypt frames. the decrypted data is stored in the rx fifo. the rxe module contains programmable filters that are programmed by the psm to accept or filter frames based on several criteri a such as receiver address, b ssid, and certain frame types. the rxe module also contains the hardware required to detect a-mpdus, parse the hea ders of the container s, and disaggregate them into component mpdus.
document no. 002-14797 rev. *h page 36 of 128 cyw4343x 5.1.1.5 ifs the ifs module contains the timers required to determine interfra me space timing including rifs timing. it also contains multip le back-off engines required to support prioritized access to the medium as specified by wmm. the interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the phy. these tim- ers provide precise timing to the txe to begin frame transmission. the txe uses this information to send response frames or per - form transmit frame-bursting (rifs or sifs separated, as within a txop). the back-off engines (for each access category) monitor channel ac tivity, in each slot duration, to determine whether to contin ue or pause the back-off counters. when the back- off counters reach 0, the txe gets notified so that it may commence frame transmis- sion. in the event of multiple back-off counters decrementing to 0 at the same time, the hardware resolves the conflict based o n pol- icies provided by the psm. the ifs module also incorporates hardware that allows the mac to enter a low-power state when operating under the ieee power- saving mode. in this mode, the mac is in a suspended state with its clock turned off. a sleep timer, whose count value is initi alized by the psm, runs on a slow clock and determines the duration over which the mac remains in this suspended state. once the timer expires, the mac is restored to its functional state. the psm upd ates the tsf timer based on th e sleep duration, ensuring that the tsf is synchronized to the network. the ifs module also contains the pta hardware that assists the psm in bluetooth coexistence functions. 5.1.1.6 tsf the timing synchronization function (tsf) module maintains the tsf timer of the mac. it also ma intains the target beacon transm is- sion time (tbtt). the tsf timer hardware, under the control of the psm, is ca pable of adopting timestamps received from beacon and probe response frames in order to ma intain synchronization with the network. the tsf module also generates trigger signals for events that are specified as offsets from the tsf timer, such as uplink and d own- link transmission times used in psmp. 5.1.1.7 nav the network allocation vector (nav) timer module is responsible for maintaining the nav information conveyed through the durati on field of mac frames. this ensures that the mac complies with the protection me chanisms specified in the standard. the hardware, under the control of the psm, maintains the nav timer and updates the timer appropriately based on received frames. this timing information is provided to the ifs modu le, which uses it as a virtual carrier-sense indication. 5.1.1.8 mac-phy interface the mac-phy interface consists of a data path interface to exchange rx/tx data from /to the phy. in addition, there is a program - ming interface, which can be controlled either by the host or the psm to co nfigure and control the phy. 5.2 phy description the cyw4343x wlan digital phy is designed to comply with ieee 802.11b/g/n single stream to provide wireless lan connectivity supporting data rates from 1 mbps to 96 mbps fo r low-power, high-performance handheld applications. the phy has been designed to meet specification requirements in the presence of interference, radio nonlinearity, and impairmen ts. it incorporates efficient implement ations of the filters, fft, and viterbi deco der algorithms. efficient algorithms have been d esigned to achieve maximum throughput and reliability, including algorithms for carrier sense/rejection, frequency/phase/timing acquisi tion and tracking, and channel estimation and tracking. the phy rece iver also contains a robust ieee 802.11b demodulator. the phy carrier sense has been tuned to provide high throughput for i eee 802.11g/ieee 802.11b hybrid netw orks with bluetooth coexis- tence. 5.2.1 phy features supports the ieee 802.11b/g/n single-stream standards. explicit ieee 802.11n transmit beamforming. supports optional greenfield mode in tx and rx. tx and rx ldpc for improved range and power efficiency. supports ieee 802.11h/d for worldwide operation. algorithms achieving low power, enhanced sensitivity, range, and reliability.
document no. 002-14797 rev. *h page 37 of 128 cyw4343x algorithms to maximize throughput performanc e in the presence of bluetooth signals. automatic gain control scheme for blocking and nonblocking application scenarios for cellular applications. closed-loop transmit power control. designed to meet fcc and other regulatory requirements. support for 2.4 ghz broadcom turboqam data rates and 20 mhz channel bandwidth. figure 27. wlan phy block diagram the phy is capable of fully calibrating the rf front-end to ex tract the highest performance. on power-up, the phy performs a fu ll calibration suite to correct for iq mismat ch and local oscillator leakage. the phy also performs periodic calibration to compen sate for any temperature related drift, thus ma intaining high-performance over time. a closed-loop transmit control algorithm mainta ins the output power at its required level and can control tx power on a per-packet basis. filters ? and ? radio ? comp frequency ? and ? timing ? synch carrier ? sense, ? agc, ? and ? rx ? fsm radio ? control ? block filters ? and ? radio ? comp afe ? and ? radio mac ? interface buffers ofdm ? demodulate viterbi ? decoder tx ? fsm pa ? comp modulation ? and ? coding modulate/ spread frame ? and ? scramble fft/ifft cck/dsss ? demodulate descramble ? and ? deframe coex
document no. 002-14797 rev. *h page 38 of 128 cyw4343x 6. wlan radio subsystem the cyw4343x includes an inte grated wlan rf transceiver that has been optimized for use in 2.4 ghz wireless lan systems. it is designed to provide low power, low cost, and robust communicat ions for applications operatin g in the globally available 2.4 ghz unlicensed ism band. the transmit and receive sections include all on-chip filtering, mixing, and gain control functions. impro ve- ments to the radio design include shared tx/rx bas eband filters and high immunity to supply noise. figure 28 shows the radio functional block diagram. figure 28. radio functional block diagram 6.1 receive path the cyw4343x has a wide dynamic range, direct conversion receiver . it employs high-order on-chip channel filtering to ensure re li- able operation in the noisy 2.4 ghz ism band. gm bt ? logen wl ? logen bt ? pll wl ? pll wlan ? bb bt ? bb clb voltage ? regulators bt ? fm lpo/ext ? lpo/rcal bt ? adc bt ? dac wl ? pa wl ? pga wl ? tx ? g \ mixer wl ? txlpf wl ? rx ? g \ mixer slna wl ? g \ lna12 bt ? lna ? load bt ? lna ? gm bt ? pa bt ? rx ? mixer bt ? tx ? mixer bt ? rxlpf bt ? txlpf shared ? xo wl ? rxlpf wl ? atx wl ? grx wl ? gtx wl ? arx bt ? tx bt ? rx bt ? adc bt ? rxlpf bt ? dac wl ? adc wl ? adc wl ? rxlpf wl ? dac wl ? dac wl ? txlpf wlrf_2g_elg wlrf_2g_rf 4 ? ~ ? 6 ? nh ? 10 ? pf recommend ? q ? = ? 40
document no. 002-14797 rev. *h page 39 of 128 cyw4343x 6.2 transmit path baseband data is modulated and upconverted to the 2.4 ghz ism band. a linear on-chip power amplifier is included, which is capa - ble of delivering high output powers while meeting ieee 802.11b/g/n specifications without the need for an external pa. this pa is supplied by an internal ldo that is directly supplied by vbat, thereby eliminating the need for a separate paldo. closed-loop o ut- put power control is integrated. 6.3 calibration the cyw4343x features dynamic on-chip ca libration, eliminating process variatio n across components. this enables the cyw4343x to be used in high-volume applications because cali bration routines are not requir ed during manufacturing testing. these calibration routines are performed per iodically during normal radio operation. au tomatic calibration examples include bas e- band filter calibration for optimum transmit and receive performance and loft calibrat ion for leakage reduction. in addition, i /q cal- ibration, r calibration, and vco calibration are performed on-chip. 7. bluetooth + fm subsystem overview the cypress cyw4343x is a bluet ooth 4.1-compliant, baseband processor and 2.4 ghz transceiver with an integrated fm/rds/ rbds receiver. it features the highest level of integration and eliminates all cr itical external component s, thus minimizing th e foot- print, power consumption, and system cost of a bluetooth plus fm radio solution. the cyw4343x is the optimal solution for any bluetooth voice and/ or data application that also requires an fm radio receiver. t he bluetooth subsystem presents a standard host controller interface (hci) via a high speed uart and pcm interface for audio. the fm subsystem supports the hci control interface as well as i 2 s, pcm, and stereo analog interfaces. the cyw4343x incorporates all bluetooth 4.1 features including secure simple pair ing, sniff subrating, and encryption pause and resume. the cyw4343x bluetooth radio transceiver provides enhanced ra dio performance to meet the mo st stringent mobile phone tem- perature applications and the tightest integr ation into mobile handsets and portable de vices. it is fully compatible with any o f the standard tcxo frequencies and provides full radio compatibility to oper ate simultaneously with gps, wlan, nfc, and cellular radios. the bluetooth transmitter also features a cla ss 1 power amplifier with class 2 capability. 7.1 features major bluetooth features of the cyw4343x include: supports key features of upcoming bluetooth standards fully supports bluetooth core sp ecification version 4.1 plus en hanced data rate (edr) features: ? adaptive frequency hopping (afh) ? quality of service (qos) ? extended synchronous connections (esco)?voice connections ? fast connect (interlaced page and inquiry scans) ? secure simple pairing (ssp) ? sniff subrating (ssr) ? encryption pause resume (epr) ? extended inquiry response (eir) ? link supervision timeout (lst) uart baud rates up to 4 mbps supports all bluetooth 4.1 packet types supports maximum bluetooth data rates over hci uart multipoint operation with up to seven active slaves ? maximum of seven simultaneous active acl links ? maximum of three simultaneous active sco and esco connections with scatternet support trigger beacon fast connect (tbfc) narrowband and wideband packet loss concealment scatternet operation with up to four active pico nets with background scan and support for scatter mode
document no. 002-14797 rev. *h page 40 of 128 cyw4343x high-speed hci uart transport su pport with low-power out-of-band bt _dev_wake and bt_h ost_wake signaling (see host controller power management on page 43 ) channel-quality driven data rate and packet type selection standard bluetooth test modes extended radio and production test mode features full support for power savings modes ? bluetooth clock request ? bluetooth standard sniff ? deep-sleep modes and software regulator shutdown tcxo input and auto-detection of all sta ndard handset clock frequencies. also s upports a low-power crystal, which can be used during power save mode for better timing accuracy. major fm radio features include: 65 mhz to 108 mhz fm bands supported (us, europe, and japan) fm subsystem control using the bluetooth hci interface fm subsystem operates fr om reference clock inputs. improved audio interface capabilities with full-featured bidirectional pcm, i 2 s, and stereo analog output. i 2 s can be master or slave. fm receiver-specific features include: excellent fm radio performance with 1 v sensitivity for 26 db (s+n)/n signal-dependent stereo/mono blending signal dependent soft mute auto search and tuning modes audio silence detection rssi and if frequency status indicators rds and rbds demodulator and decoder with filter and buffering functions automatic frequency jump 7.2 bluetooth radio the cyw4343x has an integrated radio tran sceiver that has been optimized for use in 2.4 ghz bluetooth wire less systems. it has been designed to provide low-power, low-cost, robust communicatio ns for applications operating in the globally available 2.4 gh z unlicensed ism band. it is fully compliant wit h the bluetooth radio specific ation and edr specificatio n and meets or exceeds th e requirements to provide the highest communication link quality of service. 7.2.1 transmit the cyw4343x features a fully integrated zero-if transmitter. t he baseband transmit data is gfsk-modulated in the modem block and upconverted to the 2.4 ghz ism band in the transmitter path. the transmitter path has signal f ilters, an i/q upconverter, a n out- put power amplifier, and rf filters. th e transmitter path also incorporates ? /4?dqpsk for 2 mbps and 8? dpsk for 3 mbps to sup- port edr. the transmitter section is compat ible with the bluetooth low energy specificat ion. the transmitter pa bias can also b e adjusted to provide bluetooth class 1 or class 2 operation. 7.2.2 digital modulator the digital modulator performs the data modu lation and filtering required for the gfsk, ? /4?dqpsk, and 8?dpsk signal. the fully digital modulator minimizes any frequency drift or anomalies in th e modulation characteristics of the transmitted signal and is much more stable than direct vco modulation schemes. 7.2.3 digital demodulator and bit synchronizer the digital demodulator and bit synchronizer take the low-if re ceived signal and perform an optimal frequency tracking and bit- syn- chronization algorithm.
document no. 002-14797 rev. *h page 41 of 128 cyw4343x 7.2.4 power amplifier the fully integrated pa supports class 1 or class 2 output using a highly linearized, temperature- compensated design. this prov ides greater flexibility in front-end matching and filtering. due to the linear nature of the pa combined with some integrated filte ring, exter- nal filtering is required to meet the bluetooth and regulatory harmonic and spur ious requirements. for integrated mobile handse t applications in which bluetooth is integrat ed next to the cellular radio, external filtering can be applied to achieve near-the rmal noise levels for spurious and radiated noise emis sions. the transmitter features a sophistica ted on-chip transmit signal strength ind icator (tssi) block to keep the absolute output pow er variation within a tight range acro ss process, voltage, and temperature. 7.2.5 receiver the receiver path uses a low-if scheme to downconvert the rece ived signal for demodulation in the digital demodulator and bit s yn- chronizer. the receiver path provides a high degree of linearit y, an extended dynamic range, an d high-order on-chip channel fil tering to ensure reliable operation in the noisy 2.4 ghz ism band. the front-end topology with built-in out-of-band attenuation enable s the cyw4343x to be used in most applications wi th minimal off-chip filtering. for integr ated handset operation, in which the blueto oth function is integrated close to the cellular transmitter, external filtering is requir ed to eliminate the desensitization of th e receiver by the cellular transmit signal. 7.2.6 digital demodulator and bit synchronizer the digital demodulator and bit synchronizer take the low-if rece ived signal and perform an optimal frequency tracking and bit syn- chronization algorithm. 7.2.7 receiver signal strength indicator the radio portion of the cyw4343x provides a receiver signal st rength indicator (rssi) signal to the baseband so that the contr ol- ler can take part in a bluetooth power-controlled link by providin g a metric of its own receiver signal strength to determine w hether the transmitter should increase or decrease its output power. 7.2.8 local oscillator generation local oscillator (lo) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. the lo generation subblock employs an architecture for high imm unity to lo pulling during pa operation. the cyw4343x uses an internal rf and if loop filter. 7.2.9 calibration the cyw4343x radio transceiver features an aut omated calibration scheme that is self contained in the radio. no user interactio n is required during normal operation or during manufacturing to optim ize performance. calibration optim izes the performance of all the major blocks within the radio to wi thin 2% of optimal conditions, including filter gain and phase characteristics, matching bet ween key components, and key gain blo cks. this takes into account proc ess variation and temperature va riation. calibration occurs tr ans- parently during normal operation during the se ttling time of the hops and calibrates for temperature variations as the device c ools and heats during normal operation in its environment.
document no. 002-14797 rev. *h page 42 of 128 cyw4343x 8. bluetooth baseband core the bluetooth baseband core (bbc) implements all of the time-critical functions require d for high-performance bluetooth operati on. the bbc manages the buffering, segmentation, and routing of data for all connections. it also buffers data that passes through it, handles data flow control, schedules sco/acl tx/rx transactions, monitors bluetooth slot usag e, optimally segments and pack- ages data into baseband packets, manages connection status in dicators, and composes and decodes hci packets. in addition to these functions, it independently handles hci event types and hci command types. the following transmit and receive functions are also implemented in the bbc hardware to increase the reliability and security of data before sending and receiving it over the air: symbol timing recovery, data deframing, forward error corre ction (fec), header error control (hec), cyclic redundancy check (crc), data decryption, and data dewhitening in the receiver. data framing, fec generation, hec gene ration, crc generation, key generation, dat a encryption, and data whitening in the transmitter. 8.1 bluetooth 4.1 features the bbc supports all bluetooth 4.1 fe atures, with the following benefits: dual-mode classic bluetooth and classic low energy (bt and ble) operation. low energy physical layer low energy link layer enhancements to hci for low energy low energy direct test mode 128 aes-ccm secure connection for both bt and ble note: the cyw4343x is compatible with the bluet ooth low energy operating mode, which prov ides a dramatic reduction in the power consumption of the bluetooth radio and bas eband. the primary application for this mode is to provide support for low data rate devices, such as sensors and remote controls. 8.2 link control layer the link control layer is part of the bluetooth link control fu nctions that are implemented in dedicated logic in the link cont rol unit (lcu). this layer contains the command controller that takes co mmands from the software, and othe r controllers that are activat ed or configured by the command co ntroller, to perform the link cont rol tasks. each task performs a different state in the bluetoo th link controller. major states: ? standby ? connection substates: ? page ? page scan ? inquiry ? inquiry scan ? sniff ? ble adv ? ble scan/initiation 8.3 test mode support the cyw4343x fully supports bluetooth test mode as described in part i:1 of the specification of the bl uetooth system version 3.0 . this includes the transmitter tests, normal and del ayed loopback tests, and reduced hopping sequence. in addition to the standard bluetooth test mode, the cyw4343x al so supports enhanced testing feat ures to simplify rf debugging and qualification as well as type-approv al testing. these features include: fixed frequency carrier-wave (unmodulated) transmission ? simplifies some type-appr oval measurements (japan) ? aids in transmitter performance analysis
document no. 002-14797 rev. *h page 43 of 128 cyw4343x fixed frequency constant receiver mode ? receiver output directed to an i/o pin ? allows for direct ber measurements using standard rf test equipment ? facilitates spurious emissions testing for receive mode fixed frequency constant transmission ? eight-bit fixed pattern or prbs-9 ? enables modulated signal measuremen ts with standard rf test equipment 8.4 bluetooth power management unit the bluetooth power management unit (pmu) provides power managem ent features that can be invo ked by either software through power management registers or packet handling in the bas eband core. the power management functions provided by the cyw4343x are: rf power management host controller power management bbc power management fm power management 8.4.1 rf power management the bbc generates power-down control signals for the transmit path , receive path, pll, and power amplifier to the 2.4 ghz trans - ceiver. the transceiver then processes the power-down functions accordingly. 8.4.2 host controller power management when running in uart mode, the cyw4343x can be configur ed so that dedicated signals ar e used for power management hand- shaking between the cyw4343x and the host . the basic power saving functions supported by those handshaking signals include the standard bluetooth defined power savi ngs modes and standby modes of operation. ta b l e 8 describes the power-control handshake signals used with the uart interface. table 8. power cont rol pin description signal type description bt_dev_wake i bluetooth device wake-up signal: signal from the host to the cyw4343x indicating that the host requires attention. ? asserted: the bluetooth device must wake up or remain awake. ? deasserted: the bluetooth device ma y sleep when sleep criteria are met. the polarity of this signal is software c onfigurable and can be asserted high or low. bt_host_wake o host wake-up signal. signal from the cyw 4343x to the host indicating that the cyw4343x requires attention. ? asserted: host device must wake up or remain awake. ? deasserted: host device may sleep when sleep criteria are met. the polarity of this signal is software c onfigurable and can be asserted high or low. clk_req o the cyw4343x asserts clk_req when bluetooth or wlan directs the host to turn on the reference clock. the clk_req polarity is ac tive-high. add an external 100 k ? pull-down resistor to ensure the signal is deasserted when the cyw4343x powers up or resets when vddio is present. note: pad function control register is set to 0 for these pins.
document no. 002-14797 rev. *h page 44 of 128 cyw4343x figure 29. startup signaling sequence 8.5 bbc power management the following are low-power operations for the bbc: physical layer packet-handling turns the rf on and off dynamically within transmit/receive packets. bluetooth-specified low-power connection modes: sniff and ho ld. while in these modes, t he cyw4343x runs on the low- power oscillator and wakes up after a predefined time period. hostresetx vddio lpo bt_gpio_0 ? (bt_dev_wake) bt_uart_cts_n clk_req_out bt_gpio_1 ? (bt_host_wake) bt_reg_on bt_uart_rts_n host ? ios ? configured host ? ios ? unconfigured bth ? ios ? configured bth ? ios ? unconfigured t4 t5 t3 t2 t1 notes ? : ?? t1 ? is ? the ? time ? for ? host ? to ? settle ? it?s ? ios ? after ? a ? reset. t2 ? is ? the ? time ? for ? host ? to ? drive ? bt_reg_on ? high ? after ? the ? host ? ios ? are ? configured. ? t3 ? is ? the ? time ? for ? bth ? (bluetooth) ? device ? to ? settle ? its ? ios ? after ? a ? reset ? and ? reference ? clock ? settling ? time ? has ? elapsed. t4 ? is ? the ? time ? for ? bth ? device ? to ? drive ? bt_uart_rts_n ? low ? after ? the ? host ? drives ?? bt_uart_cts_n ? low. ? this ? assumes ? the ? bth ? device ? has ? already ? completed ? initialization. t5 ? is ? the ? time ? for ? bth ? device ? to ? drive ? clk_req_out ? high ? after ? bt_reg_on ? goes ? high. ? note ? this ? pin ? is ? used ? for ? designs ? that ? use ? an ? external ? reference ? clock ? source ? from ? the ? host. ? this ? pin ? is ? irrelevant ? for ? crystal ? reference ? clock ? based ? designs ? where ? the ? bth ? device ? generates ? it?s ? own ? reference ? clock ? from ? an ? external ? crystal ? connected ? to ? it?s ? oscillator ? circuit. timing ? diagram ? assumes ? vbat ? is ? present. driven pulled bth ? device ? drives ? this ? line ? low ? indicating ? transport ? is ? ready host ? side ? drives ? this ? line ? low
document no. 002-14797 rev. *h page 45 of 128 cyw4343x a low-power shutdown feature a llows the device to be turned off while the host and any other devices in the system remain operational. when the cyw4343x is not needed in the system, th e rf and core supplies are shut down while the i/o remains powered. this allows the cyw4343x to effectively be off while keeping the i/o pins powered, so they do not draw extra current from any other i/o-connected devices. during the low-power shut-down state, provi ded vddio remains applied to the cyw4343x, all outputs are tristat ed, and most input signals are disabled. input voltages must remain within the limits defined for normal operation. this is done to prevent curren t paths or create loading on digital signals in the system and enables t he cyw4343x to be fully integrated in an embedded device to tak e full advantage of the lowest power-saving modes. two cyw4343x input signals are designed to be high-impedance input s that do not load the driving si gnal even if the chip does n ot have vddio power supplied to it: the frequency reference in put (wrf_tcxo_in) and the 32.768 khz input (lpo). when the cyw4343x is powered on from this state, it is the same as a normal power-up, and the device does not contain any information about its state from the time before it was powered down. 8.5.1 fm power management the cyw4343x fm subsystem can operate in dependently of, or in tandem with, the bluetooth rf and bbc subsystems. the fm subsystem power management scheme operates in conjunction wi th the bluetooth rf and bbc subsystems. the fm block does not have a low power state, it is either on or off. 8.5.2 wideband speech the cyw4343x provides support for wideband speech (wbs) tec hnology. the cyw4343x can perf orm subband-codec (sbc), as well as msbc, encoding and decoding of linear 16 bits at 16 khz (256 kbps rate) transferred over the pcm bus. 8.6 packet loss concealment packet loss concealment (plc) improves the apparent audio quality for systems with marginal link performance. bluetooth mes- sages are sent in packets. when a packet is lost, it creates a gap in the received audio bit-stream. packet loss can be mitigat ed in several ways: fill in zeros. ramp down the output audio signal toward zero (thi s is the method used in current bluetooth headsets). repeat the last frame (or packet) of the received bit-stream and decode it as usual (frame repeat). these techniques cause distortion and popping in the audio str eam. the cyw4343x uses a proprietary waveform extension algo- rithm to provide dramatic impr ovement in the audio quality. figure 30 and figure 31 show audio waveforms with and without packet loss concealment. cypress plc/bec algo rithms also support wideband speech. figure 30. cvsd decoder output waveform without plc packet losses causes ramp-down
document no. 002-14797 rev. *h page 46 of 128 cyw4343x figure 31. cvsd decoder output waveform after applying plc 8.6.1 codec encoding the cyw4343x can support sbc and msbc encoding and decoding for wideband speech. 8.6.2 multiple simultaneous a2dp audio streams the cyw4343x has the ability to take a single audio stream and output it to multiple bluetooth devices simultaneously. this all ows a user to share his or her music (or any audio stream) with a friend. 8.6.3 fm over bluetooth fm over bluetooth enables the cyw4343x to stream data from fm over bluetooth without requiring the host to be awake. this can significantly extend battery life for us age cases where someone is listening to fm radio on a bluetooth headset. 8.7 adaptive frequency hopping the cyw4343x gathers link quality statistics on a channel by ch annel basis to facilitate channel assessment and channel map selection. the link quality is determined us ing both rf and baseband signal processing to provide a more accurate frequency-hop map. 8.8 advanced blueto oth/wlan coexistence the cyw4343x includes advanced coexistenc e technologies that are only possible with a bluetooth/wlan integrated die solution. these coexistence technol ogies are targeted at small form-factor platforms, such as cell pho nes and media play ers, including ap pli- cations such as vowlan + sco and video-over-wlan + high fidelity bt stereo. support is provided for platforms that share a single antenna bet ween bluetooth and wlan. dual-antenna applications are also supported. the cyw4343x radio architecture allows for lossles s simultaneous bluetooth and wlan reception for shared antenna applications. this is possible only via an integrated solution (shared lna and joint agc algorithm). it has superior performanc e ver- sus implementations that nee d to arbitrate between bluetooth and wlan reception. the cyw4343x integrated solution enables mac-layer signaling (fir mware) and a greater degree of sharing via an enhanced coex- istence interface. information is exchanged between the bl uetooth and wlan cores without host processor involvement. the cyw4343x also supports transmit power control (tpc) on the st a together with standard bluetooth tpc to limit mutual inter- ference and receiver desensitization. pree mption mechanisms are utilized to prevent ap transmissions from colliding with blueto oth frames. improved channel classification techniques have been implem ented in bluetooth for faster and more accurate detection an d elimination of interferers (incl uding non-wlan 2.4 ghz interference). the bluetooth afh classification is also enhanced by the wlan core?s channel information. 8.9 fast connection (interlaced page and inquiry scans) the cyw4343x supports page scan and inquiry scan modes that si gnificantly reduce the average inquiry response and connection times. these scanning modes are compatible with the bluetooth version 2.1 page and inquiry procedures.
document no. 002-14797 rev. *h page 47 of 128 cyw4343x 9. microprocessor and me mory unit for bluetooth the bluetooth microprocessor core is based on the arm co rtex-m3 32-bit risc processo r with embedded ice-rt debug and jtag interface units. it runs software from the link co ntrol (lc) layer up to the hos t controller interface (hci). the arm core is paired with a memory unit that contains 57 6 kb of rom for program storage and boot rom, and 160 kb of ram for data scratch-pad and patch ram code. the internal rom allows for flexibility during power-on reset (por) to enable the same device to be used in various configurations. at power-up, the lo wer-layer protocol stack is exec uted from the internal rom memo ry. external patches may be applied to the rom-based firmware to pr ovide flexibility for bug fixes or feature additions. these patc hes may be downloaded from the host to the cyw4343x through the uart transports. 9.1 ram, rom, and patch memory the cyw4343x bluetooth core has 160 kb of internal ram wh ich is mapped between general purpose scratch-pad memory and patch memory, and 576 kb of rom used for the lower-layer protocol stack, test mode software, and boot rom. the patch memory is used for bug fixes and feature additions to rom memory code. 9.2 reset the cyw4343x has an integrated power-on reset circuit that resets all circuits to a known power-on state. the bt por circuit is out of reset after bt_reg_on goes high. if bt_reg_on is low, then the por circuit is held in reset. 10. bluetooth peripheral transport unit 10.1 pcm interface the cyw4343x supports two independent pcm in terfaces that share pins with the i 2 s interfaces. the pcm interface on the cyw4343x can connect to linear pcm codec devices in master or slave mode. in master mode, the cyw4343x generates the pcm_clk and pcm_sync signals, and in slave mode, these signals are provided by another master on the pcm interface and are inputs to the cyw4343x. the configuration of the pcm interface may be adjusted by th e host through the use of vendor-specific hci commands. 10.1.1 slot mapping the cyw4343x supports up to three simultaneous full-duplex sco or esco channels through the pcm interface. these three channels are time-multiplexed onto the single pcm interface by us ing a time-slotting scheme where the 8 khz or 16 khz audio sam - ple interval is divided into as many as 16 slots. the number of slots is dependent on the sele cted interface rate of 128 khz, 5 12 khz, or 1024 khz. the corresponding number of slot s for these interface rates is 1, 2, 4, 8, and 16, respectively. transmit and rece ive pcm data from an sco channel is always mapped to the same slot. th e pcm data output driver trista tes its output on unused slots to allow other devices to share the same pcm interface signals. the data output driver tristates its output after the falling e dge of the pcm clock during the last bit of the slot. 10.1.2 frame synchronization the cyw4343x supports both short- and long-frame synchronization in both master and slave mode s. in short-frame synchroniza- tion mode, the frame synchronization signal is an active-high pu lse at the audio frame rate that is a single-bit period in widt h and is synchronized to the rising edge of the bit clock. the pcm slav e looks for a high on the falling edge of the bit clock and expec ts the first bit of the first slot to start at the next rising edge of the clock. in long-frame synchronization mode, the frame synchr onization sig- nal is again an active-high pulse at the audio frame rate; howev er, the duration is three bit per iods and the pulse starts coin cident with the first bit of the first slot. 10.1.3 data formatting the cyw4343x may be configured to generate and accept severa l different data formats. for conventional narrowband speech mode, the cyw4343x uses 13 of the 16 bits in each pcm frame. t he location and order of these 13 bi ts can be configured to sup- port various data formats on the pcm interface. the remaining th ree bits are ignored on the input and may be filled with 0?s, 1 ?s, a sign bit, or a programmed value on the ou tput. the default format is 13-bit 2?s comple ment data, left justified, and clocked ms b first.
document no. 002-14797 rev. *h page 48 of 128 cyw4343x 10.1.4 wideband speech support when the host encodes wideband speech (wbs) packets in trans parent mode, the encoded packets are transferred over the pcm bus for an esco voice connection. in this mo de, the pcm bus is typically configured in master mode for a 4 khz sync rate with 1 6- bit samples, resulting in a 64 kbps bit rate. the cyw4343x also supports slave transparent mode using a proprietary rate-matchi ng scheme. in sbc-code mode, linear 16-bit data at 16 kh z (256 kbps rate) is transferred over the pcm bus. 10.1.5 multiplexed bluetooth and fm over pcm in this mode of operation, the cyw4343x multiplexes both fm and bluetooth audio pcm channels over the same interface, reduc- ing the number of required i/os. this mode of operation is initiated through an hci command from the host. the data stream form at contains three channels: a bluetooth channel followed by two fm ch annels (audio left and right). in this mode of operation, the bus data rate only supports 48 khz operation per channel with 16 bits sent for each channel. this is done to allow the low data rat e blue- tooth data to coexist in the same interface as the higher speed i 2 s data. to accomplish this, the bluetooth data is repeated six times for 8 khz data and three times for 16 khz data. an initial sync pulse on the pcm_sync line is used to indicate the beginning of the frame. to support multiple bluetooth audio streams within the bluetooth channel, both 16 khz and 8 khz streams can be multiplexed. thi s mode of operation is only supported when the bluetooth host is the master. figure 32 shows the operation of the multiplexed trans- port with three simultaneous sco connections. to accommodate additional sco channels, the transport clock speed is increased. to change between modes of operation, the transport mu st be halted and restarted in the new configuration. figure 32. functional multiplex data diagram pcm_sync pcm_in pcm_out fm ? right fm ? left fm ? right fm ? left bt ? sco ? 1 ? tx bt ? sco ? 2 ? tx bt ? sco ? 3 ? tx bt ? sco ? 1 ? rx bt ? sco ? 2 ? rx bt ? sco ? 3 ? rx 1 ? frame pcm_clk 16 ? bits ? per ? sco ? frame ? clk 16 ? bits ? per ? frame ? 16 ? bits ? per ? frame ? each ? sco ? channel ? duplicates ? the ? data ? 6 ? times. ?? each ? wbs ? frame ? duplicates ? the ? data ? 3 ? times ? per ? frame.
document no. 002-14797 rev. *h page 49 of 128 cyw4343x 10.1.6 pcm interface timing 10.1.6.1 short frame sync, master mode figure 33. pcm timing diagram (short frame sync, master mode) table 9. pcm interface timing specificat ions (short frame sync, master mode) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync delay 0 ? 25 ns 5 pcm_out delay 0 ? 25 ns 6 pcm_in setup 8 ? ? ns 7 pcm_in hold 8 ? ? ns 8 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0 ? 25 ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 pcm_in 6 8 high ? impedance 7
document no. 002-14797 rev. *h page 50 of 128 cyw4343x 10.1.6.2 short frame sync, slave mode figure 34. pcm timing diagram (short frame sync, slave mode) table 10. pcm interface timing specificat ions (short frame sync, slave mode) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync setup 8 ? ? ns 5 pcm_sync hold 8 ? ? ns 6 pcm_out delay 0 ? 25 ns 7 pcm_in setup 8 ? ? ns 8 pcm_in hold 8 ? ? ns 9 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0 ? 25 ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 6 pcm_in 7 9 high ? impedance 8
document no. 002-14797 rev. *h page 51 of 128 cyw4343x 10.1.6.3 long frame sync, master mode figure 35. pcm timing diagram (long frame sync, master mode) table 11. pcm interface timing specifications (long frame sync, master mode) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync delay 0 ? 25 ns 5 pcm_out delay 0 ? 25 ns 6 pcm_in setup 8 ? ? ns 7 pcm_in hold 8 ? ? ns 8 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0 ? 25 ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 pcm_in 6 8 high ? impedance 7 bit ? 0 bit ? 0 bit ? 1 bit ? 1
document no. 002-14797 rev. *h page 52 of 128 cyw4343x 10.1.6.4 long frame sync, slave mode figure 36. pcm timing diagram (long frame sync, slave mode) 10.2 uart interface the cyw4343x shares a single uart for bluetooth and fm. the uart is a standard 4-wire interface (rx, tx, rts, and cts) with adjustable baud rates from 9600 bps to 4.0 mbps. the interface fe atures an automatic baud rate det ection capability that return s a baud rate selection. alternatively, the baud rate may be selected through a vendor-specific uart hci command. the uart has a 1040-byte receive fifo and a 1040-byte transmit fifo to support edr. access to the fifos is conducted through the advanced high performance bus (ahb) in terface through either dma or the cpu. the uart supp orts the bluetooth 4.1 uart hci specification: h4 and h5. th e default baud rate is 115.2 kbaud. the uart supports the 3-wire h5 uart transport as described in the bl uetooth specification ( three-wire uart transport layer ). compared to h4, the h5 uart transport reduces the number of signal lines required by eliminating the cts and rts signals. the cyw4343x uart can perform xon/xoff flow control and includes hardware support for the serial line input protocol (slip). it can also perform a wake-on activity function. for example, acti vity on the rx or cts inputs can wake the chip from a sleep s tate. normally, the uart baud rate is set by a configuration record do wnloaded after device reset or by automatic baud rate detection , and the host does not need to adjust the baud rate. support for changing the baud rate during normal hci uart operation is included through a vendor-specific command th at allows the host to adjust the contents of the baud rate registers. the cyw4343x uarts operate correctly with the host uart as long as the co mbined baud rate error of the two devices is within 2% (see ta b l e 1 3 ). table 12. pcm interface timing specifications (long frame sync, slave mode) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync setup 8 ? ? ns 5 pcm_sync hold 8 ? ? ns 6 pcm_out delay 0 ? 25 ns 7 pcm_in setup 8 ? ? ns 8 pcm_in hold 8 ? ? ns 9 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0 ? 25 ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 6 pcm_in 7 9 high ? impedance 8 bit ? 0 bit ? 0 bit ? 1 bit ? 1
document no. 002-14797 rev. *h page 53 of 128 cyw4343x uart timing is defined in figure 37 and ta b l e 1 4 . figure 37. uart timing table 13. example of common baud rates desired rate actual rate error (%) 4000000 4000000 0.00 3692000 3692308 0.01 3000000 3000000 0.00 2000000 2000000 0.00 1500000 1500000 0.00 1444444 1454544 0.70 921600 923077 0.16 460800 461538 0.16 230400 230796 0.17 115200 115385 0.16 57600 57692 0.16 38400 38400 0.00 28800 28846 0.16 19200 19200 0.00 14400 14423 0.16 9600 9600 0.00 table 14. uart timi ng specifications ref no. characteristics minimum typical maximum unit 1 delay time, uart_cts_n low to uart_txd valid ? ? 1.5 bit periods 2 setup time, uart_cts_n high before midpoint of stop bit ? ? 0.5 bit periods 3 delay time, midpoint of stop bit to uart_rts_n high ? ? 0.5 bit periods uart_cts_n uart_rxd uart_rts_n 1 2 midpoint ? of ? stop ? bit uart_txd midpoint ? of ? stop ? bit 3
document no. 002-14797 rev. *h page 54 of 128 cyw4343x 10.3 i 2 s interface the cyw4343x supports an independent i 2 s digital audio port for high-fidelity fm audio or bluetooth audio. the i 2 s interface sup- ports both master and slave modes. the i 2 s signals are: i 2 s clock: i 2 s sck i 2 s word select: i 2 s ws i 2 s data out: i 2 s sdo i 2 s data in: i 2 s sdi i 2 s sck and i 2 s ws become outputs in master mode and inputs in slave mode, while i 2 s sdo is always an output. the channel word length is 16 bits and the data is ju stified so that the msb of the left-cha nnel data is aligned with the msb of the i 2 s bus, per the i 2 s specification. the msb of ea ch data word is transmitted one bit-clock cycle after the i 2 s ws transition, sync hronous with the fall- ing edge of the bit clock. left-ch annel data is transmitted when i 2 s ws is low, and right-channel data is transmitted when i 2 s ws is high. data bits sent by the cyw4343x are synchronized with the falling edge of i2s_sck and should be sampled by the receiver on the rising edge of i2s_ssck. the clock rate in master mode is either of the following: 48 khz x 32 bits per frame = 1.536 mhz 48 khz x 50 bits per frame = 2.400 mhz the master clock is generated from the inpu t reference clock using an n/m clock divider. in slave mode, clock rates up to 3.072 mhz are supported. 10.3.1 i 2 s timing note: timing values specified in table 15 are relative to high and low threshold levels table 15. timing for i 2 s transmitters and receivers transmitter receiver notes lower limit upper limit lower limit upper limit min. max. min. max. min. max. min. max. clock period t t tr ???t r ???1 master mode: clock generated by transmitter or receiver. high t hc 0.35t tr ???0.35t tr ???2 low t lc 0.35t tr ???0.35t tr ???2 slave mode: clock accepted by transmitter or receiver. high t hc ?0.35t tr ? ? ? 0.35t tr ??3 low t lc ?0.35t tr ? ? ? 0.35t tr ??3 rise time t rc ? ? 0.15t tr ?????4 transmitter delay t dtr ???0.8t????5 hold time t htr 0???????4 receiver setup time t sr ?????0.2t r ??6 hold time t hr ?????0??6
document no. 002-14797 rev. *h page 55 of 128 cyw4343x note: the system clock period t must be greater than t tr and t r because both the transmitter and receiver have to be able to handle the data transfer rate. at all data rates in master mode, the transm itter or receiver generates a clock signal with a fixed mark/space ratio. for this reason, t hc and t lc are specified with respect to t. in slave mode, the transmitter and receiver need a clock sign al with minimum high and low peri ods so that they can detect the signal. as long as the minimu m periods are greater than 0.35t r , any clock that meets the requirements can be used. because the delay (t dtr ) and the maximum transmitter speed (defined by t tr ) are related, a fast transmitter driven by a slow clock edge can result in t dtr not exceeding t rc , which means t htr becomes zero or negative. th erefore, the transmitter has to guarantee that t htr is greater than or equal to zero, as long as the clock rise-time, t rc , does not exceed t rcmax , where t rcmax is not less than 0.15t tr . to allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and t, always giving the receiver sufficient setup time. the data setup and hold time must not be less than the specified receiver setup and hold time. note: the time periods specified in figure 38 and figure 39 are defined by the transmitter speed. the receiver specifications must match transmitter performance. figure 38. i 2 s transmitter timing sd ? and ? ws sck v l = ? 0.8v t lc > 0.35t t rc * t hc > 0.35t t v h = ? 2.0v t htr > 0 t dtr < 0.8t t ? = ? clock ? period t tr = ? minimum ? allowed ? clock ? period ? for ? transmitter t ? = ? t tr * ? t rc is ? only ? relevant ? for ? transmitters ? in ? slave ? mode.
document no. 002-14797 rev. *h page 56 of 128 cyw4343x figure 39. i 2 s receiver timing 11. fm receiver subsystem 11.1 fm radio the cyw4343x includes a completely integrated fm radio rece iver with rds/rbds covering all fm bands from 65 mhz to 108 mhz. the receiver is controlled through comm ands on the hci. fm received audio is avai lable as a stereo analog output or in dig ital form through i 2 s or pcm. the fm radio operates fr om the external clock reference. 11.2 digital fm audio interfaces the fm audio can be transmitted via the shared pcm and i 2 s pins, and the sampling rate is programmable. the cyw4343x sup- ports a three-wire pcm or i 2 s audio interface in either a master or slave configur ation. the master or slav e configuration is selected using vendor specific commands ov er the hci interface. in addition, multiple samp ling rates are supported, derived from either the fm or bluetooth clocks. in master mode, t he clock rate is eith er of the following: 48 khz x 32 bits per frame = 1.536 mhz 48 khz x 50 bits per frame = 2.400 mhz in slave mode, clock rates up to 3.072 mhz are supported. 11.3 analog fm audio interfaces the demodulated fm audio signal is available as line-level analog stereo output, generated by twin internal high snr audio dacs . 11.4 fm over bluetooth the cyw4343x can output received fm audio onto bluetooth using one of following thre e links: esco, wbs, or a2dp. for all link types, after a link has been established, the host processor c an enter sleep mode while the cyw4343x streams fm audio to the remote bluetooth device, thus mini mizing system current consumption. 11.5 esco in this use case, the stereo fm audio is downsampled to 8 khz an d a mono or stereo stream is s ent through the bl uetooth esco li nk to a remote bluetooth device, typically a headset. two bl uetooth voice connections must be used to transport stereo. 11.6 wideband speech link in this case, the stereo fm audio is downsampled to 16 khz and a mono or stereo stream is sent through the bluetooth wideband speech link to a remote bluetooth device, typically a headset. tw o bluetooth voice connections must be used to transport stereo . sd ? and ? ws sck v l = ? 0.8v t lc > 0.35t t hc > 0.35 t v h = ? 2.0v t hr > 0 t sr > 0.2t t ? = ? clock ? period t r = ? minimum ? allowed ? clock ? period ? for ? transmitter t ? > ? t r
document no. 002-14797 rev. *h page 57 of 128 cyw4343x 11.7 a2dp in this case, the stereo fm audio is encoded by the on-chip sbc encoder and transported as an a2dp link to a remote bluetooth device. sampling rates of 48 khz, 44.1 khz, and 32 khz joint stereo are support ed. an a2dp lite stack is implemented in the cyw4343x to support this use case, which eliminates the need to route the sbc-encoded audio back to the host to create the a2dp packets. 11.8 autotune and search algorithms the cyw4343x supports a number of fm sear ch and tune functions, allowing the host to implement many convenient user func- tions by accessing the broadcom fm stack. tune to play?allows the fm receiver to be programmed to a specific frequency. search for snr > threshold?ch ecks the power level of the av ailable channel and the estima ted snr of the channel to help achieve precise control of the expected sound quality for the selected fm channel. specifically, the host can adjust its snr requirements to retrieve a signal wit h a specific sound quality, or adjust this to return the weakest channels. alternate frequency jump?allows the fm receiver to automatica lly jump to an alternate fm channel that carries the same information, but has a better snr. for example, when travel ing, a user may pass through a region where a number of channels carry the same station. when the user passes from on e area to the next, the fm receiver can automatically switch to another channel with a stronger signal to spare the user from having to manual ly change the channel to continue listen- ing to the same station. 11.9 audio features a number of features are implemented in the cyw4343x to provide the best possible audio experience for the user. mono/stereo blend or switch?the cyw4343x provides automatic cont rol of the stereo or mono settings based on the fm signal carrier-to-noise ratio (c/n). this feature is used to maintain the best po ssible audio snr based on the fm channel condition. two modes of operation are supported: ? blend: in this mode, fine control of stereo separation is used to achieve optimal audio qu ality over a wide range of input c/n. the amount of separati on is fully programmable. in figure 40 , the separation is programmed to maintain a mini- mum 50 db snr across the blend range. ? switch: in this mode, the audio switches from full stereo to fu ll mono at a predetermined level to maintain optimal audio quality. the stereo-to-mono switch point and the mono-to-stereo switch points ar e fully programmable to provide the desired amount of audio snr. in figure 41 , the switch point is progra mmed to switch to mono to maintain a 40 db snr.
document no. 002-14797 rev. *h page 58 of 128 cyw4343x figure 40. blending and switching usage figure 41. blending and switching separation soft mute?improves the user experience by dynamically muting the output audio proportionate to the fm signal c/n. this prevents a blast of static to the user. the mute characteristic is fully programmable to accommodate fine tuning of the out- put signal level. an example mute characteristic is shown in figure 42 . input ? c/n ? (db) audio ? snr ? (db) channel ? separation ? (db) input ? c/n ? (db)
document no. 002-14797 rev. *h page 59 of 128 cyw4343x figure 42. soft muting characteristic high cut?a programmable high-cut filter is provided to reduce the amount of high-frequency nois e caused by static in the output audio signal. like the soft mute ci rcuit, it is fully programmable to provi de any amount of high cut based on the fm signal c/n. audio pause detect?the fm receiver monitors the magnitude of the audio signal and notifies the host through an inter- rupt when the magnitude of the signal has fallen below the threshold set fo r a programmable period. this feature can be used to provide alternate frequency jumps during periods of silenc e to minimize disturbances to the listener. filtering tech- niques are used within the audio pause detection block to pr ovide more robust presence-to-silence detection and silence- to-presence detection. automatic antenna tuning?the cyw4343x has an on-chip au tomatic antenna tuning network. when used with a single off-chip inductor, the on-chip circuitry automatically chooses an optimal on-chip matching component to obtain the highest signal strength for the desired frequency. the high-q nature of this matching network simultaneously provides out-of-band blocking protection as well as a reduction of radiated spuri ous emissions from the fm antenna. it is designed to accommo- date a wide range of external wire antennas. 11.10 rds/rbds the cyw4343x integrates a rds/rbds modem, the decoder includ es programmable filtering and buffering functions. the rds/ rbds data can be read out through the hci interface. in addition, the rds/rbds receive fu nctionality supports the following: block decoding, error correction, and synchronization a flywheel synchronization feature, allowing the host to set par ameters for acquisition, maintenance, and loss of sync. (it is possible to set up the cy w4343x such that synchr onization is achieved when a minimu m of two good blocks (error free) are decoded in sequence. the number of good blocks required for sync is programmable.) storage capability up to 126 blocks of rds data full or partial block-b match detection with host interruption audio pause detection with programmable parameters program identification (pi) code detection with host interruption automatic frequency jumping block-e filtering soft muting audio ? gain ? (db) input ? c/n ? (db)
document no. 002-14797 rev. *h page 60 of 128 cyw4343x signal dependent mono/stereo blending 12. cpu and global functions 12.1 wlan cpu and memory subsystem the cyw4343x includes an integrated arm cortex-m3 processor with internal ram and rom. the arm cortex-m3 processor is a low-power processor that features low gate count, low inte rrupt latency, and low-cost debugging. it is intended for deeply embe dded applications that require fast interrupt response features. the processor implements the arm architecture v7-m with support for the thumb-2 instruction set. arm cortex-m3 prov ides a 30% performance gain over arm7tdmi. at 0.19 w/mhz, the cortex-m3 is the most power efficient gener al purpose microprocessor available, outperforming 8- and 16-bit devices on mips/w. it supports integrated sleep modes. arm cortex-m3 uses multiple technologies to reduce cost throu gh improved memory utilization, reduced pin overhead, and reduced silicon area. arm cortex-m3 supp orts independent buses for code and data acce ss (icode/dcode and system buses). arm cor- tex-m3 supports extensive debug features incl uding real-time tracing of program execution. on-chip memory for the cpu includes 512 kb sram and 640 kb rom. 12.2 one-time pr ogrammable memory various hardware configuration parameters ma y be stored in an internal 4096-bit one-time programmable (otp) memory, which is read by system soft ware after a device reset. in addition, customer-specific parameters, including the system vendor id and the mac address, can be stored, depending on the specific board design. the initial state of all bits in an unprogr ammed otp device is 0. after any bit is programmed to a 1, it cannot be reprogrammed to 0. the entire otp array can be programmed in a single write cycle using a utility provided with t he broadcom wlan manufacturing test tools. alternatively, multip le write cycles can be used to selectively program specific byte s, but only bits which are sti ll in the 0 state can be alte red during each pr ogramming cycle. prior to otp memory programming, all values should be verified using the appropriate editable nvram.txt file, which is provided with the reference board design package. docum entation on the otp development process is available on the broadcom customer sup- port portal (http://www .broadcom.com/support). 12.3 gpio interface five general purpose i/o (gpio) pins are available on the cyw4343x that can be used to connect to various external devices. gpios are tristated by default. subsequently, they can be programme d to be either input or output pins via the gpio control reg ister. they can also be programmed to have in ternal pull-up or pull-down resistors. gpio_0 is normally used as a wl_host_wake signal. the cyw4343x supports a 2-wire coexistenc e configuration using gpio_1 and gpio_2 . the cyw4343x supports 2-wire, 3-wire, and 4-wire coexistence configur ations using gpio_1 through gp io_4. the signal functions of gpio_1 through gpio_4 are pro- grammable to support the thr ee coexistence configurations. 12.4 external coexistence interface the cyw4343x supports a 2-wire, 3-wire, and 4-wire coexistence interfaceinterfaces to enable signaling between the device and a n external colocated wireless device in order to manage wireless medium sharing for optimal performance. the external colocated device can be any of the following ics: gps, wimax, lte, or uwb. an lte ic is used in this section for illustration. 12.4.1 2-wire coexistence figure 43 shows a 2-wire lte coexistence example. the follow ing definitions apply to the gpios in the figure: gpio_1: wlan_seci_tx output to an lte ic. gpio_2: wlan_seci_rx input from an lte ic.
document no. 002-14797 rev. *h page 61 of 128 cyw4343x figure 43. 2-wire coexistence interface to an lte ic see figure 37 on page 53 and table 14, ?uart timing specifications,? on page 53 for uart timing. 12.4.2 3-wire and 4-wire coexistence interfaces figure 44 and figure 45 show 3-wire and 4-wire lte coexistence examples, re spectively. the following definitions apply to the gpios in the figures: for the 3-wire coexistence interface: gpio_2: wlan priority output to an lte ic. gpio_3: lte_rx input from an lte ic. gpio_4: lte_tx input from an lte ic. for the 4-wire coexistence interface: gpio_1: wlan priority output to an lte ic. gpio_2: lte frame sync input from an lte ic. this gpio applies only to the 4-wi re coexistence interface. gpio_3: lte_rx input from an lte ic. gpio_4: lte_tx input from an lte ic. figure 44. 3-wire coexistence interface to an lte ic wlan coexistence ? interface lte/ic uart_in uart_out bt/fm notes: ? ? or?ing ? to ? generate ? ism_rx_priority ? for ? ercx_txconf ? or ? bt_rx_priority ? is ? achieved ? by ? setting ? the ? gpio ? mask ? registers ? appropriately. ? wlan_seci_out ? and ? wlan_seci_in ? are ? multiplexed ? on ? the ? gpios. gpio_1 wlan_seci_tx wlan_seci_rx gpio_2 cyw4343x note: ? or?ing ? to ? generate ? wcn_priority ? for ? ercx_txconf ? or ? bt_rx_priority ? is ? achieved ? by ? setting ? the ? gpio ? mask ? registers ? appropriately. wlan lte/ic bt/fm gpio_2 gpio_3 gpio_4 coexistence ? interface lte_rx lte_tx wlan ? priority cyw4343x
document no. 002-14797 rev. *h page 62 of 128 cyw4343x figure 45. 4-wire coexistence interface to an lte ic 12.5 jtag interface the cyw4343x supports the ieee 1149.1 jtag boundary scan standard over sdio for performing device package and pcb assembly testing during manufacturing. in addition, the jtag inte rface allows cypress to assist customers by using proprietary debug and characterization test tools during board bring-up. theref ore, it is highly recommended to provide access to the jtag pins by means of test points or a header on all pcb designs. 12.6 uart interface one uart interface can be enabled by software as an alternate f unction on the jtag pins. uart_rx is available on the jtag_tdi pin, and uart_tx is available on the jtag_tdo pin. the uart is primarily for debugging during development. by ad ding an external rs-232 transceiver, this uart enables the cyw4343x to operate as rs-232 data terminat ion equipment (dte) for exchanging and man aging data with other serial devices. it is compatible with the industry standard 16550 uart, and it provides a fifo size of 64 8 in each direction. note: ? or?ing ? to ? generate ? wcn_priority ? for ? ercx_txconf ? or ? bt_rx_priority ? is ? achieved ? by ? setting ? the ? gpio ? mask ? registers ? appropriately. wlan lte/ic bt/fm gpio_1 gpio_2 gpio_3 coexistence ? interface wlan ? priority lte_frame_sync lte_rx gpio_4 lte_tx cyw4343x
document no. 002-14797 rev. *h page 63 of 128 cyw4343x 13. wlan software architecture 13.1 host softwa re architecture the host driver (dhd) provides a transpar ent connection between the host operating system and the cyw4343x media (for exam- ple, wlan) by presenting a network driver interface to the ho st operating system and communicating with the cyw4343x over an interface-specific bus (spi, sdio, and so on) to: forward transmit and receive frames between t he host network stack and the cyw4343x device. pass control requests from the host to the cyw4343x device, returning the cyw4343x device responses. the driver communicates with the cyw4343x over the bus using a control channel and a data channel to pass control messages and data messages. the actual message format is based on the bdc protocol. 13.2 device software architecture the wireless device, protocol, and bus drivers are run on t he embedded arm processor using a broadcom-defined operating sys- tem called hndrte, which transfers data over a propriety br oadcom format over the sdio/spi interface between the host and device (bdc/lmac). the data portion of the format consists of ieee 802.11 frames wra pped in a broadcom encapsulation. the host architecture provides all missing functionality between a network device and the broadcom device interface. the host can also b e customized to provide functionality be tween the broadcom device interface and a full network device interface. this transfer requires a message-oriented (framed) interconnect between the host and dev ice. the sdio bus is an addressed bus? each host-initiated bus operation contains an explicit device target address?and does not natively support a higher-level data frame concept. broadcom has implemented a hardw are/software message encapsulation schem e that ignores the bus operation code address and prefixes each frame with a 4- byte length tag for framing. the device pres ents a packet-level interface over which d ata, control, and asynchronous event (fro m the device) packets are supported. the data and control packets received from the bus are initially processed by the bus driver and then passed on to the protocol driver. if the packets are data packets, they are transferred to the wireless device driver (and out through its medium), and a data packet received from the device medium follows the same path in the reverse direction. if the pa ckets are control packets, the proto- col header is decoded by the protocol driv er. if the packets are wireless ioctl packets , the ioctl api of the wireless driver i s called to configure the wireless device. the microcode running in the d11 core processes all time-critical tasks. 13.3 remote downloader when the cyw4343x powers up, the dhd initializes and downloads the firmware to run in the device. figure 46. wlan software architecture 13.4 wireless conf iguration utility the device driver that supports the cypress ieee 802.11 family of wireless soluti ons provides an input/output control (ioctl) i nter- face for making advanced configuration settings. the ioctl interf ace makes it possible to make settings that are normally not p os- sible when using just the native operating system-specific ieee 802.11 configuration mech anisms. the utility uses ioctls to que ry or set a number of different driver/chip operating properties. spi/sdio bdc/lmac protocol wireless device driver d11 core dhd host driver
document no. 002-14797 rev. *h page 64 of 128 cyw4343x 14. pinout and signal descriptions 14.1 ball map figure 48 on page 65 shows the 63-ball wlbga ball map. figure 47 shows the 74-ball wlbga ball map. figure 49 on page 66 shows the 153-bump wlcsp. figure 47. 74-ball wlbga ball map (bottom view) abcd e f gh jk l m 1 bt_uart_ rxd bt_dev_ wake bt_host_ wake fm_rf_in bt_vco_v dd bt_if_vdd bt_pavdd wlrf_2g_ elg wlrf_2g_ rf wlrf_pa_ vdd 1 2 bt_uart_ txd bt_uart_ cts_n fm_out1 fm_out2 fm_rf_vd d btfm_pll _vdd btfm_pll _vss bt_if_vss wlrf_lna _gnd wlrf_ge neral_gn d wlrf_pa_ gnd wlrf_vd d_ 1p35 2 3 bt_i2s_ ws bt_i2s_do bt_uart_ rts_n vddc fm_rf_vs s bt_vco_v ss wlrf_gpi o wlrf_vc o_gnd wlrf_xta l_ vdd1p2 3 4 bt_i2s_cl k bt_pcm_o ut bt_pcm_i n vssc bt_gpio_3 vddc wlrf_afe _gnd gpio_3 wlrf_xta l_gnd wlrf_xta l_xop 4 5 bt_pcm_c lk bt_pcm_s ync sys_vddi o wpt_1p8 wpt_3p3 lpo_in bt_gpio_4 bt_gpio_5 vssc gpio_4 gpio_2 wlrf_xta l_xon 5 6 sr_vlx pmu_avs s vout_cld o vout_lnl do bt_reg_o n wcc_vddi o wl_reg_ on gpio_1 gpio_0 sdio_dat a_0 sdio_cmd clk_req 6 7 sr_pvss sr_vddb at5v ldo_vdd1 p5 vout_3p3 ldo_vdd bat5v sdio_dat a_1 sdio_dat a_3 sdio_dat a_2 sdio_clk 7 abcd e f gh jk l m
document no. 002-14797 rev. *h page 65 of 128 cyw4343x figure 48. 63-ball wlbga ball map (bottom view) abcdefgh jklm 1 bt_uart_ rxd bt_dev_ wake bt_host_ wake fm_rf_in bt_vco_ vdd bt_if_ vdd bt_pavdd wlrf_ 2g_elg wlrf_ 2g_rf wlrf_ pa_vdd 1 2 bt_uart_ txd bt_uart_ cts_n fm_out1 fm_out2 fm_rf_ vdd btfm_ pll_vdd btfm_ pll_vss bt_if_vss wlrf_ lna_gnd wlrf_ general_ gnd wlrf_pa_ gnd wlrf_vd d_ 1p35 2 3 bt_uart_ rts_n vddc fm_rf_vs s bt_vco_v ss wlrf_gpi o wlrf_vc o_gnd wlrf_xta l_vdd1p2 3 4 bt_pcm_ out bt_pcm_i n vssc vddc wlrf_afe _gnd wlrf_xta l_gnd wlrf_xta l_xop 4 5 bt_pcm_ clk bt_pcm_ sync lpo_in vssc gpio_2 wlrf_xta l_xon 5 6 sr_vlx pmu_avs s vout_cld o vout_lnl do bt_reg_o n wcc_vddi o wl_reg_ on gpio_1 gpio_0 sdio_ data_0 sdio_cmd clk_req 6 7 sr_pvss sr_ vddbat5v ldo_vdd1 p5 vout_3p3 ldo_ vddbat5v sdio_ data_1 sdio_ data_3 sdio_ data_2 sdio_clk 7 abcdefgh jklm
document no. 002-14797 rev. *h page 66 of 128 cyw4343x figure 49. 153-bump wlcsp (top view)(4343w) 14.2 wlbga ball list in ball nu mber order with x-y coordinates ta b l e 1 6 provides ball numbers and names in ball number order. the table includes the x and y coordinates for a top view with a (0,0) center. table 16. cyw4343x wlbga ball li st ? ordered by ball number ball number ball name x coordinate y coordinate a1 bt_uart_rxd ?1200.006 2199.996 a2 bt_uart_txd ?799.992 2199.996
document no. 002-14797 rev. *h page 67 of 128 cyw4343x a3 bt_i2s_ws or bt_pcm_sync ?399.996 2199.996 a4 bt_i2s_clk or bt_pcm_clk 0 2199.996 a5 bt_pcm_clk or bt_i2s_clk 399.996 2199.996 a6 sr_vlx 799.992 2199.978 a7 sr_pvss 1199.988 2199.978 b1 bt_dev_wake ?1200.006 1800 b2 bt_uart_cts_n ?799.992 1800 b3 bt_i2s_do or bt_pcm_out ?399.996 1800 b4 bt_pcm_out or bt_i2s_do 0 1800 b5 bt_pcm_sync or bt_i2s_ws 399.996 1800 b6 pmu_avss 799.992 1799.982 b7 sr_vbat5v 1199.988 1799.982 c1 bt_host_wake ?1200.006 1399.995 c2 fm_out1 ?799.992 1399.986 c3 bt_uart_rts_n ?399.996 1399.995 c4 bt_pcm_in or bt_i2s_di 0 1399.995 c5 sys_vddio 399.996 1399.986 c6 vout_cldo 799.992 1399.986 c7 ldo_vdd15v 1199.988 1399.986 d2 fm_out2 ?799.992 999.99 d3 vddc ?399.996 999.999 d4 vssc 0 999.999 d5 wpt_1p8 399.996 999.99 d6 vout_lnldo 799.992 999.99 e1 fm_rf_in ?1199.988 599.994 e2 fm_rf_vdd ?799.992 599.994 e3 fm_rf_vss ?399.996 599.994 e5 wpt_3p3 399.996 599.994 e6 bt_reg_on 799.992 599.994 e7 vout_3p3 1199.988 599.994 f1 bt_vco_vdd ?1199.988 199.998 f2 btfm_pll_vdd ?799.992 199.998 f4 bt_gpio_3 0 199.998 f5 lpo_in 399.996 199.998 f6 wcc_vddio 800.001 199.998 f7 ldo_vbat5v 1199.988 199.998 g1 bt_if_vdd ?1199.988 ?199.998 g2 btfm_pll_vss ?799.992 ?199.998 table 16. cyw4343x wlbga ball list ? ordered by ball number (cont.) ball number ball name x coordinate y coordinate
document no. 002-14797 rev. *h page 68 of 128 cyw4343x g4 vddc 0 ?199.998 g5 bt_gpio_4 399.996 ?199.998 g6 wl_reg_on 800.001 ?199.998 h1 bt_pavdd ?1199.988 ?599.994 h2 bt_if_vss ?799.992 ?599.994 h3 bt_vco_vss ?399.996 ?599.994 h4 wlrf_afe_gnd 0 ?599.994 h5 bt_gpio_5 399.996 ?599.994 h6 gpio_1 800.001 ?599.994 h7 sdio_data_1 1200.006 ?599.994 j1 wlrf_2g_elg ?1199.988 ?999.99 j2 wlrf_lna_gnd ?799.992 ?999.99 j3 wlrf_gpio ?399.996 ?999.99 j5 vssc 399.996 ?999.999 j6 gpio_0 800.001 ?999.999 j7 sdio_data_3 1200.006 ?999.999 k1 wlrf_2g_rf ?1199.988 ?1399.986 k2 wlrf_general_gnd ?799.992 ?1399.986 k4 gpio_3 0 ?1399.995 k5 gpio_4 399.996 ?1399.995 k6 sdio_data_0 800.001 ?1399.995 l2 wlrf_pa_gnd ?799.992 ?1799.982 l3 wlrf_vco_gnd ?399.996 ?1799.982 l4 wlrf_xtal_gnd 0 ?1799.982 l5 gpio_2 399.996 ?1799.991 l6 sdio_cmd 800.001 ?1799.991 l7 sdio_data_2 1200.006 ?1799.991 m1 wlrf_pa_vdd ?1199.988 ?2199.978 m2 wlrf_vdd_1p35 ?799.992 ?2199.978 m3 wlrf_xtal_vdd1p2 ?399.996 ?2199.978 m4 wlrf_xtal_xop 0 ?2199.978 m5 wlrf_xtal_xon 399.996 ?2199.978 m6 clk_req 800.001 ?2199.996 m7 sdio_clk 1200.006 ?2199.996 table 16. cyw4343x wlbga ball list ? ordered by ball number (cont.) ball number ball name x coordinate y coordinate
document no. 002-14797 rev. *h page 69 of 128 cyw4343x 14.3 wlbga ball list in ball nu mber order with x-y coordinates ta b l e 1 7 provides ball numbers and names in ball number order. the t able includes the x and y coordinates for a top view with a (0,0) center. table 17. cyw4343x wlbga ball list ? ordered by ball number ball number ball name x coordinate y coordinate a1 bt_uart_rxd ?1200.006 2199.996 a2 bt_uart_txd ?799.992 2199.996 a5 bt_pcm_clk or bt_i2s_clk 399.996 2199.996 a6 sr_vlx 799.992 2199.978 a7 sr_pvss 1199.988 2199.978 b1 bt_dev_wake ?1200.006 1800 b2 bt_uart_cts_n ?799.992 1800 b4 bt_pcm_out or bt_i2s_do 0 1800 b5 bt_pcm_sync or bt_i2s_ws 399.996 1800 b6 pmu_avss 799.992 1799.982 b7 sr_vbat5v 1199.988 1799.982 c1 bt_host_wake ?1200.006 1399.995 c2 fm_out1 ?799.992 1399.986 c3 bt_uart_rts_n ?399.996 1399.995 c4 bt_pcm_in or bt_i2s_di 0 1399.995 c6 vout_cldo 799.992 1399.986 c7 ldo_vdd15v 1199.988 1399.986 d2 fm_out2 ?799.992 999.99 d3 vddc ?399.996 999.999 d4 vssc 0 999.999 d6 vout_lnldo 799.992 999.99 e1 fm_rf_in ?1199.988 599.994 e2 fm_rf_vdd ?799.992 599.994 e3 fm_rf_vss ?399.996 599.994 e6 bt_reg_on 799.992 599.994 e7 vout_3p3 1199.988 599.994 f1 bt_vco_vdd ?1199.988 199.998 f2 btfm_pll_vdd ?799.992 199.998 f5 lpo_in 399.996 199.998 f6 wcc_vddio 800.001 199.998 f7 ldo_vbat5v 1199.988 199.998 g1 bt_if_vdd ?1199.988 ?199.998 g2 btfm_pll_vss ?799.992 ?199.998 g4 vddc 0 ?199.998
document no. 002-14797 rev. *h page 70 of 128 cyw4343x 14.4 wlcsp bump list in bump order with x-y coordinates g6 wl_reg_on 800.001 ?199.998 h1 bt_pavdd ?1199.988 ?599.994 h2 bt_if_vss ?799.992 ?599.994 h3 bt_vco_vss ?399.996 ?599.994 h4 wlrf_afe_gnd 0 ?599.994 h6 gpio_1 800.001 ?599.994 h7 sdio_data_1 1200.006 ?599.994 j1 wlrf_2g_elg ?1199.988 ?999.99 j2 wlrf_lna_gnd ?799.992 ?999.99 j3 wlrf_gpio ?399.996 ?999.99 j5 vssc 399.996 ?999.999 j6 gpio_0 800.001 ?999.999 j7 sdio_data_3 1200.006 ?999.999 k1 wlrf_2g_rf ?1199.988 ?1399.986 k2 wlrf_general_gnd ?799.992 ?1399.986 k6 sdio_data_0 800.001 ?1399.995 l2 wlrf_pa_gnd ?799.992 ?1799.982 l3 wlrf_vco_gnd ?399.996 ?1799.982 l4 wlrf_xtal_gnd 0 ?1799.982 l5 gpio_2 399.996 ?1799.991 l6 sdio_cmd 800.001 ?1799.991 l7 sdio_data_2 1200.006 ?1799.991 m1 wlrf_pa_vdd ?1199.988 ?2199.978 m2 wlrf_vdd_1p35 ?799.992 ?2199.978 m3 wlrf_xtal_vdd1p2 ?399.996 ?2199.978 m4 wlrf_xtal_xop 0 ?2199.978 m5 wlrf_xtal_xon 399.996 ?2199.978 m6 clk_req 800.001 ?2199.996 m7 sdio_clk 1200.006 ?2199.996 table 18. cyw4343x wlcsp bump list ? ordered by bump number bump number bump name bump view (0,0 center of die) top view (0,0 center of die) x coordinate y coordinate x coordinate y coordinate 1 bt_uart_rxd 1228.248 2133.594 ?1228.248 2133.594 2 bt_vddc_iso_2 944.082 2195.919 ?944.082 2195.919 3 bt_pcm_clk or bt_i2s_clk 238.266 2275.020 ?238.266 2275.020 table 17. cyw4343x wlbga ball list ? ordered by ball number (cont.) ball number ball name x coordinate y coordinate
document no. 002-14797 rev. *h page 71 of 128 cyw4343x 4 bt_tm1 ?327.438 2275.020 327.438 2275.020 5 bt_gpio_3 662.544 2133.594 ?662.544 2133.594 6 bt_dev_wake 379.692 2133.594 ?379.692 2133.594 7 bt_uart_rts_n 1086.822 1992.168 ?1086.822 1992.168 8 bt_gpio_4 521.118 1992.168 ?521.118 1992.168 9 bt_vddc_iso_1 ?44.586 1992.168 44.586 1992.168 10 bt_gpio_5 ?327.438 1992.168 327.438 1992.168 11 bt_host_wake 1228.248 1850.742 ?1228.248 1850.742 12 bt_uart_txd 945.396 1850.742 ?945.396 1850.742 13 bt_gpio_2 662.544 1850.742 ?662.544 1850.742 14 bt_vddc 379.692 1850.742 ?379.692 1850.742 15 bt_i2s_clk or bt_pcm_clk ?186.012 1850.742 186.012 1850.742 16 bt_vddc 516.501 1717.578 ?516.501 1717.578 17 bt_pcm_sync or bt_i2s_ws 1086.822 1709.316 ?1086.822 1709.316 18 bt_i2s_ws or bt_pcm_sync 238.266 1709.316 ?238.266 1709.316 19 bt_pcm_out or bt_i2s_do ?327.438 1709.316 327.438 1709.316 20 bt_pcm_in or bt_i2s_di 662.544 1567.890 ?662.544 1567.890 21 vssc 96.840 1567.890 ?96.840 1567.890 22 bt_uart_cts_n ?186.012 1567.890 186.012 1567.890 23 bt_i2s_di or bt_pcm_in 238.266 1426.464 ?238.266 1426.464 24 bt_i2s_do or bt_pcm_out ?327.438 1426.464 327.438 1426.464 25 vssc 96.840 1285.038 ?96.840 1285.038 26 bt_vddc 518.391 1189.863 ?518.391 1189.863 27 vssc 238.266 860.760 ?238.266 860.760 28 bt_vddc ?44.586 719.334 44.586 719.334 29 vssc 110.286 561.303 ?110.286 561.303 30 vssc ?327.438 436.482 327.438 436.482 31 bt_vddc 521.118 436.473 ?521.118 436.473 32 vssc 238.266 153.630 ?238.266 153.630 33 vssc ?44.586 153.630 44.586 153.630 34 bt_vddc 229.986 ?185.976 ?229.986 ?185.976 35 bt_pavss 1185.471 ?455.270 ?1185.471 ?455.270 36 vssc ?875.142 ?836.352 875.142 ?836.352 37 fm_dac_vout1 1243.031 1443.096 ?1243.031 1443.096 38 fm_dac_avss 1043.033 1443.096 ?1043.033 1443.096 39 fm_pllavss 820.485 1275.098 ?820.485 1275.098 40 fm_dac_vout2 1243.031 1243.098 ?1243.031 1243.098 41 fm_dac_avdd 1043.033 1243.098 ?1043.033 1243.098 42 fm_vcovss 1252.220 1043.100 ?1252.220 1043.100 table 18. cyw4343x wlcsp bump list ? ordered by bump number (cont.) bump number bump name bump view (0,0 center of die) top view (0,0 center of die) x coordinate y coordinate x coordinate y coordinate
document no. 002-14797 rev. *h page 72 of 128 cyw4343x 43 fm_plldvdd1p2 820.485 960.593 ?820.485 960.593 44 fm_vcovdd1p2 1120.383 892.373 ?1120.383 892.373 45 fm_rfvdd1p2 1274.787 764.213 ?1274.787 764.213 46 fm_rfvss 1172.988 563.990 ?1172.988 563.990 47 fm_ifvss 972.990 563.990 ?972.990 563.990 48 fm_ifdvdd1p2 772.304 563.990 ?772.304 563.990 49 fm_rfinmain 1276.551 383.225 ?1276.551 383.225 50 bt_dvss 686.628 160.911 ?686.628 160.911 51 bt_ifvdd1p2 886.626 148.775 ?886.626 148.775 52 bt_agpio 1185.471 ?55.274 ?1185.471 ?55.274 53 bt_pavdd2p5 1185.462 ?255.272 ?1185.462 ?255.272 54 bt_lnavdd1p2 781.893 ?263.768 ?781.893 ?263.768 55 bt_lnavss 781.893 ?463.766 ?781.893 ?463.766 56 bt_pllvss 429.885 ?499.995 ?429.885 ?499.995 57 bt_vcovdd1p2 1185.471 ?655.268 ?1185.471 ?655.268 58 bt_vcovss 786.393 ?663.764 ?786.393 ?663.764 59 bt_pllvdd1p2 429.885 ?699.993 ?429.885 ?699.993 60 wrf_afe_gnd 583.250 ?999.990 ?583.250 ?999.990 61 wrf_rfin_elg_2g 1262.642 ?1006.290 ?1262.642 ?1006.290 62 wrf_rx2g_gnd 1082.642 ?1006.290 ?1082.642 ?1006.290 63 wrf_rfio_2g 1206.990 ?1458.198 ?1206.990 ?1458.198 64 wrf_general_gnd 628.713 ?1590.210 ?628.713 ?1590.210 65 wrf_pa_gnd3p3 986.531 ?1649.615 ?986.531 ?1649.615 66 wrf_vco_gnd 451.188 ?1682.370 ?451.188 ?1682.370 67 wrf_gpaio_out 799.992 ?1729.224 ?799.992 ?1729.224 68 wrf_pmu_vdd1p35 612.878 ?1800.135 ?612.878 ?1800.135 69 wrf_pa_gnd3p3 986.531 ?1829.615 ?986.531 ?1829.615 70 wrf_pa_vdd3p3 1249.686 ?2016.945 ?1249.686 ?2016.945 71 wrf_pa_vdd3p3 1069.686 ?2016.945 ?1069.686 ?2016.945 72 wrf_xtal_gnd1p2 274.613 ?2086.677 ?274.613 ?2086.677 73 wrf_xtal_vdd1p2 75.519 ?2106.621 ?75.519 ?2106.621 74 wrf_xtal_xop 311.126 ?2298.978 ?311.126 ?2298.978 75 wrf_xtal_xon 131.126 ?2298.978 ?131.126 ?2298.978 76 lpo_in 96.840 2133.594 ?96.840 2133.594 77 wcc_vddio ?186.012 2133.594 186.012 2133.594 78 vssc 96.813 1850.742 ?96.813 1850.742 79 wcc_vddio ?44.586 1002.186 44.586 1002.186 80 gpio_12 ?1299.420 436.482 1299.420 436.482 81 gpio_11 ?1157.994 295.056 1157.994 295.056 table 18. cyw4343x wlcsp bump list ? ordered by bump number (cont.) bump number bump name bump view (0,0 center of die) top view (0,0 center of die) x coordinate y coordinate x coordinate y coordinate
document no. 002-14797 rev. *h page 73 of 128 cyw4343x 82 gpio_9 ?1016.568 153.630 1016.568 153.630 83 gpio_10 ?1299.420 153.630 1299.420 153.630 84 gpio_8 ?1157.994 12.204 1157.994 12.204 85 vssc ?186.012 ?129.222 186.012 ?129.222 86 vddc ?468.864 ?129.222 468.864 ?129.222 87 gpio_7 ?1299.420 ?129.222 1299.420 ?129.222 88 vssc ?610.290 ?270.648 610.290 ?270.648 89 gpio_6 ?1157.994 ?270.648 1157.994 ?270.648 90 vssc ?44.586 ?412.074 44.586 ?412.074 91 gpio_4 ?1299.420 ?412.074 1299.420 ?412.074 92 vssc 96.840 ?553.500 ?96.840 ?553.500 93 vddc ?186.012 ?553.500 186.012 ?553.500 94 gpio_5 ?1157.994 ?553.500 1157.994 ?553.500 95 vddc ?44.586 ?694.926 44.586 ?694.926 96 wl_vddp_iso ?733.716 ?694.926 733.716 ?694.926 97 gpio_2 ?1299.420 ?694.926 1299.420 ?694.926 98 gpio_3 ?1157.994 ?836.352 1157.994 ?836.352 99 wcc_vddio ?1016.568 ?977.778 1016.568 ?977.778 100 gpio_0 ?1299.420 ?977.778 1299.420 ?977.778 101 gpio_1 ?1157.994 ?1119.204 1157.994 ?1119.204 102 vssc ?720.954 ?1120.266 720.954 ?1120.266 103 wcc_vddio ?1016.568 ?1260.630 1016.568 ?1260.630 104 sdio_cmd ?1299.420 ?1260.630 1299.420 ?1260.630 105 gpio_14 ?137.700 ?1268.568 137.700 ?1268.568 106 vssc ?841.113 ?1402.056 841.113 ?1402.056 107 vddc ?1016.568 ?1543.482 1016.568 ?1543.482 108 sdio_clk ?1299.420 ?1543.482 1299.420 ?1543.482 109 gpio_15 109.152 ?1551.420 ?109.152 ?1551.420 110 packageoption_0 ?173.700 ?1551.420 173.700 ?1551.420 111 vssc ?843.237 ?1682.775 843.237 ?1682.775 112 sdio_data_0 ?1157.994 ?1684.908 1157.994 ?1684.908 113 packageoption_1 ?32.274 ?1692.846 32.274 ?1692.846 114 vddc ?1016.568 ?1826.334 1016.568 ?1826.334 115 sdio_data_1 ?1299.420 ?1826.334 1299.420 ?1826.334 116 packageoption_2 109.152 ?1834.272 ?109.152 ?1834.272 117 jtag_sel ?173.700 ?1834.272 173.700 ?1834.272 118 sdio_data_2 ?1157.994 ?1967.760 1157.994 ?1967.760 119 gpio_13 ?232.227 ?2056.131 232.227 ?2056.131 120 wcc_vddio ?1016.568 ?2109.186 1016.568 ?2109.186 table 18. cyw4343x wlcsp bump list ? ordered by bump number (cont.) bump number bump name bump view (0,0 center of die) top view (0,0 center of die) x coordinate y coordinate x coordinate y coordinate
document no. 002-14797 rev. *h page 74 of 128 cyw4343x 121 vssc ?1299.420 ?2109.186 1299.420 ?2109.186 122 sdio_data_3 ?1157.994 ?2250.612 1157.994 ?2250.612 123 sr_pvss ?739.130 2274.984 739.130 2274.984 124 sr_pvss ?1021.973 2274.984 1021.973 2274.984 125 vssc ?597.708 2133.563 597.708 2133.563 126 sr_vlx ?880.551 2133.563 880.551 2133.563 127 sr_vlx ?1163.394 2133.563 1163.394 2133.563 128 sr_vlx ?739.130 1992.141 739.130 1992.141 129 sr_vddbat5v ?1021.973 1992.141 1021.973 1992.141 130 sr_vddbat5v ?1304.816 1992.141 1304.816 1992.141 131 pmu_avss ?597.708 1850.720 597.708 1850.720 132 sr_vddbat5v ?880.551 1850.720 880.551 1850.720 133 ldo_vdd1p5 ?1021.973 1709.298 1021.973 1709.298 134 vout_cldo ?880.551 1567.877 880.551 1567.877 135 ldo_vdd1p5 ?1163.394 1567.877 1163.394 1567.877 136 vout_cldo ?739.130 1426.455 739.130 1426.455 137 wcc_vddio ?597.708 1285.034 597.708 1285.034 138 vout_lnldo ?880.551 1285.034 880.551 1285.034 139 vout_3p3 ?1163.394 1285.034 1163.394 1285.034 140 sys_vddio ?739.130 1143.612 739.130 1143.612 141 ldo_vddbat5v ?1304.816 1143.612 1304.816 1143.612 142 vssc ?597.708 1002.191 597.708 1002.191 143 vout_3p3_sense ?880.551 1002.191 880.551 1002.191 144 vout_3p3 ?1163.394 1002.191 1163.394 1002.191 145 wpt_1p8 ?739.130 860.769 739.130 860.769 146 wpt_3p3 ?1021.973 860.769 1021.973 860.769 147 ldo_vddbat5v ?1304.816 860.769 1304.816 860.769 148 wl_reg_on ?597.708 719.348 597.708 719.348 149 bt_reg_on ?880.551 719.348 880.551 719.348 150 wl_vddm_iso ?875.142 12.204 875.142 12.204 151 pll_vssc ?116.586 ?985.716 116.586 -985.716 152 pll_vddc 29.286 ?1130.076 ?29.286 ?1130.076 153 clk_req 238.266 1992.168 ?238.266 1992.168 table 18. cyw4343x wlcsp bump list ? ordered by bump number (cont.) bump number bump name bump view (0,0 center of die) top view (0,0 center of die) x coordinate y coordinate x coordinate y coordinate
document no. 002-14797 rev. *h page 75 of 128 cyw4343x 14.5 wlbga ball list ordered by ball name ta b l e 1 9 provides the ball numbers and names in ball name order. table 19. cyw4343x wlbga ball list ? ordered by ball name ball name ball number bt_dev_wake b1 bt_gpio_3 f4 bt_gpio_4 g5 bt_gpio_5 h5 bt_host_wake c1 bt_i2s_clk or bt_pcm_clk a4 bt_i2s_do or bt_pcm_out b3 bt_i2s_ws or bt_pcm_sync a3 bt_if_vdd g1 bt_if_vss h2 bt_pavdd h1 bt_pcm_clk or bt_i2s_clk a5 bt_pcm_in or bt_i2s_di c4 bt_pcm_out or bt_i2s_do b4 bt_pcm_sync or bt_i2s_ws b5 bt_reg_on e6 bt_uart_cts_n b2 bt_uart_rts_n c3 bt_uart_rxd a1 bt_uart_txd a2 bt_vco_vdd f1 bt_vco_vss h3 btfm_pll_vdd f2 btfm_pll_vss g2 clk_req m6 fm_out1 c2 fm_out2 d2 fm_rf_in e1 fm_rf_vdd e2 fm_rf_vss e3 gpio_0 j6 gpio_1 h6 gpio_2 l5 gpio_3 k4 gpio_4 k5 ldo_vdd1p5 c7 ldo_vddbat5v f7 lpo_in f5 pmu_avss b6 sdio_clk m7 sdio_cmd l6 sdio_data_0 k6 sdio_data_1 h7 sdio_data_2 l7 sdio_data_3 j7 sr_pvss a7 sr_vddbat5v b7 sr_vlx a6 sys_vddio c5 vddc d3 vddc g4 vout_3p3 e7 vout_cldo c6 vout_lnldo d6 vssc d4 vssc j5 wcc_vddio f6 wl_reg_on g6 wlrf_2g_elg j1 wlrf_2g_rf k1 wlrf_afe_gnd h4 wlrf_general_gnd k2 wlrf_gpio j3 wlrf_lna_gnd j2 wlrf_pa_gnd l2 wlrf_pa_vdd m1 wlrf_vco_gnd l3 wlrf_vdd_1p35 m2 wlrf_xtal_gnd l4 wlrf_xtal_vdd1p2 m3 wlrf_xtal_xon m5 wlrf_xtal_xop m4 wpt_1p8 d5 wpt_3p3 e5 ball name ball number
document no. 002-14797 rev. *h page 76 of 128 cyw4343x 14.6 wlbga ball list ordered by ball name ta b l e 2 0 provides the ball numbers and names in ball name order. table 20. cyw4343x wlbga ball list ? ordered by ball name ball name ball number bt_dev_wake b1 bt_host_wake c1 bt_if_vdd g1 bt_if_vss h2 bt_pavdd h1 bt_pcm_clk or bt_i2s_clk a5 bt_pcm_in or bt_i2s_di c4 bt_pcm_out or bt_i2s_do b4 bt_pcm_sync or bt_i2s_ws b5 bt_reg_on e6 bt_uart_cts_n b2 bt_uart_rts_n c3 bt_uart_rxd a1 bt_uart_txd a2 bt_vco_vdd f1 bt_vco_vss h3 btfm_pll_vdd f2 btfm_pll_vss g2 clk_req m6 fm_out1 c2 fm_out2 d2 fm_rf_in e1 fm_rf_vdd e2 fm_rf_vss e3 gpio_0 j6 gpio_1 h6 gpio_2 l5 ldo_vdd1p5 c7 ldo_vddbat5v f7 lpo_in f5 pmu_avss b6 sdio_clk m7 sdio_cmd l6 sdio_data_0 k6 sdio_data_1 h7 sdio_data_2 l7 sdio_data_3 j7 sr_pvss a7 sr_vddbat5v b7 sr_vlx a6 vddc d3 vddc g4 vout_3p3 e7 vout_cldo c6 vout_lnldo d6 vssc d4 vssc j5 wcc_vddio f6 wl_reg_on g6 wlrf_2g_elg j1 wlrf_2g_rf k1 wlrf_afe_gnd h4 wlrf_general_gnd k2 wlrf_gpio j3 wlrf_lna_gnd j2 wlrf_pa_gnd l2 wlrf_pa_vdd m1 wlrf_vco_gnd l3 wlrf_vdd_1p35 m2 wlrf_xtal_gnd l4 wlrf_xtal_vdd1p2 m3 wlrf_xtal_xon m5 wlrf_xtal_xop m4 ball name ball number
document no. 002-14797 rev. *h page 77 of 128 cyw4343x 14.7 wlcsp bump list ordered by name ta b l e 2 1 provides the bump numbers and names in bump name order. table 21. cyw4343x wlcsp bump list ? ordered by bump name bump name bump number(s) bt_agpio 52 bt_dev_wake 6 bt_dvss 50 bt_gpio_2 13 bt_gpio_3 5 bt_gpio_4 8 bt_gpio_5 10 bt_host_wake 11 bt_i2s_clk or bt_pcm_clk 15 bt_i2s_di or bt_pcm_in 23 bt_i2s_do or bt_pcm_out 24 bt_i2s_ws or bt_pcm_sync 18 bt_ifvdd1p2 51 bt_lnavdd1p2 54 bt_lnavss 55 bt_pavdd2p5 53 bt_pavss 35 bt_pcm_clk or bt_i2s_clk 3 bt_pcm_in or bt_i2s_di 20 bt_pcm_out or bt_i2s_do 19 bt_pcm_sync or bt_i2s_ws 17 bt_pllvdd1p2 59 bt_pllvss 56 bt_reg_on 149 bt_tm1 4 bt_uart_cts_n 22 bt_uart_rts_n 7 bt_uart_rxd 1 bt_uart_txd 12 bt_vcovdd1p2 57 bt_vcovss 58 bt_vddc 14, 16, 26, 28, 31, 34 bt_vddc_iso_1 9 bt_vddc_iso_2 2 clk_req 153 fm_dac_avdd 41 fm_dac_avss 38 fm_dac_vout1 37 fm_dac_vout2 40 fm_ifdvdd1p2 48 fm_ifvss 47 fm_pllavss 39 fm_plldvdd1p2 43 fm_rfinmain 49 fm_rfvdd1p2 45 fm_rfvss 46 fm_vcovdd1p2 44 fm_vcovss 42 gpio_0 100 gpio_1 101 gpio_2 97 gpio_3 98 gpio_4 91 gpio_5 94 gpio_6 89 gpio_7 87 gpio_8 84 gpio_9 82 gpio_10 83 gpio_11 81 gpio_12 80 gpio_13 119 gpio_14 105 gpio_15 109 jtag_sel 117 ldo_vdd1p5 133, 135 ldo_vddbat5v 141, 147 lpo_in 76 packageoption_0 110 packageoption_1 113 packageoption_2 116 pll_vddc 152 pll_vssc 151 pmu_avss 131 bump name bump number(s)
document no. 002-14797 rev. *h page 78 of 128 cyw4343x sdio_clk 108 sdio_cmd 104 sdio_data_0 112 sdio_data_1 115 sdio_data_2 118 sdio_data_3 122 sr_pvss 123, 124 sr_vddbat5v 129, 130, 132 sr_vlx 126, 127, 128 sys_vddio 140 vddc 86, 93, 95, 107, 114 vout_3p3 139, 144 vout_3p3_sense 143 vout_cldo 134, 136 vout_lnldo 138 vssc 21, 25, 27, 29, 30, 32, 33, 36, 78, 85, 88, 90, 92, 102, 106, 111, 121, 125, 142 wcc_vddio 77, 79, 99, 103, 120, 137 wl_reg_on 148 wl_vddm_iso 150 wl_vddp_iso 96 wpt_1p8 145 wpt_3p3 146 wrf_afe_gnd 60 wrf_general_gnd 64 wrf_gpaio_out 67 wrf_pa_gnd3p3 65, 69, 70, 71 wrf_pmu_vdd1p35 68 wrf_rfin_elg_2g 61 wrf_rfio_2g 63 wrf_rx2g_gnd 62 wrf_vco_gnd 66 wrf_xtal_gnd1p2 72 wrf_xtal_vdd1p2 73 wrf_xtal_xon 75 wrf_xtal_xop 74 bump name bump number(s)
document no. 002-14797 rev. *h page 79 of 128 cyw4343x 14.8 signal descriptions ta b l e 2 2 provides the wlbga package signal descriptions. table 22. wlbga signal descriptions signal name wlbga ball type description rf signal interface wlrf_2g_rf k1 o 2.4 ghz bt and wlan rf output port sdio bus interface sdio_clk m7 i sdio clock input sdio_cmd l6 i/o sdio command line sdio_data_0 k6 i/o sdio data line 0 sdio_data_1 h7 i/o sdio data line 1. sdio_data_2 l7 i/o sdio data line 2. also used as a strapping option (see table 26 on page 87 ). sdio_data_3 j7 i/o sdio data line 3 note: per section 6 of the sdio specification, 10 to 100 k ? pull-ups are required on the four data lines and the cmd line. this requirement must be met during all oper ating states by using exter nal pull-up resistors or properly programming internal sdio host pull-ups. wlan gpio interface wlrf_gpio j3 i/o test pin. not connected in normal operation. clocks wlrf_xtal_xon m5 o xtal oscillator output wlrf_xtal_xop m4 i xtal oscillator input clk_req m6 o external system cloc k request?used when the system clock is not provided by a de dicated crystal (for example, when a shared tcxo is used). asserted to indicate to the host that the clock is required. shared by bt, and wlan. lpo_in f5 i external sleep clock input (32.768 khz). if an external 32.768 khz clock cannot be provided, pull this pin low. however, ble will be always on and cannot go to deep sleep. fm receiver fm_out1 c2 o fm analog output 1 fm_out2 d2 o fm analog output 2 fm_rf_in e1 i fm radio antenna port fm_rf_vdd e2 i fm power supply bluetooth pcm bt_pcm_clk or bt_i2s_clk a5 i/o pcm or i 2 s clock; can be master (output) or slave (input) bt_pcm_in or bt_i2s_di c4 i pcm or i 2 s data input sensing bt_pcm_out or bt_i2s_do b4 o pcm or i 2 s data output bt_pcm_sync or bt_i2s_ws b5 i/o pcm sync or i2s_ws; can be master (output) or slave (input) bluetooth gpio bt_gpio_3 f4 i/o bluetooth general pur pose i/o.wpt_intb to wireless charging pmu. bt_gpio_4 g5 i/o bluetooth general purpose i/o.bsc_sda to/from wireless charging pmu. bt_gpio_5 h5 i/o bluetooth general purpose i/o.bsc_scl from wireless charging pmu.
document no. 002-14797 rev. *h page 80 of 128 cyw4343x bluetooth uart and wake bt_uart_cts_n b2 i uart clear-to-send. active-low clear-to-send signal for the hci uart interface. bt_uart_rts_n c3 o uart request-to-send. active-low request-to-send signal for the hci uart interface. bt_uart_rxd a1 i uart serial input. serial data input for the hci uart interface. bt_uart_txd a2 o uart serial output. serial data output for the hci uart interface. bt_dev_wake b1 i/o dev_wake or general-purpose i/o signal. bt_host_wake c1 i/o host_wake or general-purpose i/o signal. note: by default, the bluetooth bt wake signals provide gpio/wake functi onality, and the uart pins provide uart functionality. through software configuration, the pcm interface can also be routed over the bt_wake/uart signals as follows: ? pcm_clk on the uart_rts_n pin ? pcm_out on the uart_cts_n pin ? pcm_sync on the bt_host_wake pin ? pcm_in on the bt_dev_wake pin in this case, the bt hci transport included sleep signaling will oper ate using uart_rxd and uart_txd; that is, using a 3-wire u art transport. bluetooth/fm i 2 s bt_i2s_clk or bt_pcm_clk a4 i/o i 2 s or pcm clock; can be master (output) or slave (input) bt_i2s_do or bt_pcm_out b3 i/o i 2 s or pcm data output bt_i2s_ws or bt_pcm_sync a3 i/o i 2 s ws or pcm sync; can be master (output) or slave (input) miscellaneous wl_reg_on g6 i used by pmu to power up or power down the internal regulators used by the wlan section. also, when deasserted, this pin holds the wlan section in reset. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. bt_reg_on e6 i used by pmu to power up or power down the internal regulators used by the bluetooth/fm section. also, when deasserted, this pin holds the bluetooth/fm section in reset. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. wpt_3p3 e5 n/a not used. do not connect to this pin. wpt_1p8 d5 n/a not used. do not connect to this pin. gpio_0 j6 i/o programmable gpio pins. this pin becomes an output pin when it is used as wlan_host_wake/out-of-band signal. gpio_1 h6 i/o programmable gpio pins gpio_2 l5 i/o programmable gpio pins gpio_3 k4 i/o programmable gpio pins gpio_4 k5 i/o programmable gpio pins wlrf_2g_elg j1 i connect to an external inductor. see the reference schematic for details. table 22. wlbga signal descriptions (cont.) signal name wlbga ball type description
document no. 002-14797 rev. *h page 81 of 128 cyw4343x integrated voltage regulators sr_vddbat5v b7 i sr vbat input power supply sr_vlx a6 o cbuck switching regulator output. see table 42 on page 107 for details of the inductor and capacitor required on this output. ldo_vddbat5v f7 i ldo vbat ldo_vdd1p5 c7 i lnldo input vout_lnldo d6 o output of low-noise lnldo vout_cldo c6 o output of core ldo bluetooth power supplies bt_pavdd h1 i bluetooth pa power supply bt_if_vdd g1 i bluetooth if block power supply btfm_pll_vdd f2 i bluetooth rf pll power supply bt_vco_vdd f1 i bluetooth rf power supply table 22. wlbga signal descriptions (cont.) signal name wlbga ball type description
document no. 002-14797 rev. *h page 82 of 128 cyw4343x [4343w] ta b l e 2 3 provides the wlcsp package signal descriptions. power supplies wlrf_xtal_vdd1p2 m3 i xtal oscillator supply wlrf_pa_vdd m1 i power amplifier supply wcc_vddio f6 i vddio input supply. connect to vddio. sys_vddio[4343s+4343w+43cs4343w1] c5 i vddio input supply. connect to vddio. wlrf_vdd_1p35 m2 i lnldo input supply vddc d3, g4 i core supply for wlan and bt. vout_3p3 e7 o 3.3v output supply. se e the reference schematic for details. ground bt_if_vss h2 i 1.2v bluetooth if block ground btfm_pll_vss g2 i bluetooth/fm rf pll ground bt_vco_vss h3 i 1.2v bluetooth rf ground fm_rf_vss e3 i fm rf ground pmu_avss b6 i quiet ground sr_pvss a7 i switcher-power ground vssc d4, j5 i core ground for wlan and bt wlrf_afe_gnd h4 i afe ground wlrf_lna_gnd j2 i 2.4 ghz internal lna ground wlrf_general_gnd k2 i miscellaneous rf ground wlrf_pa_gnd l2 i 2.4 ghz pa ground wlrf_vco_gnd l3 i vco/lo generator ground wlrf_xtal_gnd l4 i xtal ground table 23. wlcsp signal descriptions signal name wlcsp bump type description or instruction rf signal interface wrf_rfin_elg_2g 61 i connect to an external inductor. see the reference schematic for details. wrf_rfio_2g 63 i/o 2.4 ghz bt and wlan rf input/output port sdio bus interface sdio_clk 108 i sdio clock input sdio_cmd 104 i/o sdio command line sdio_data_0 112 i/o sdio data line 0 sdio_data_1 115 i/o sdio data line 1. sdio_data_2 118 i/o sdio data line 2. also used as a strapping option (see table 26 on page 87 ). sdio_data_3 122 i/o sdio data line 3 note: per section 6 of the sdio specification, 10 to 100 k ? pull-ups are required on the four data lines and the cmd line. this requirement must be met during all oper ating states by using external pull-up re sistors or properly programming internal sdio host pull-ups. table 22. wlbga signal descriptions (cont.) signal name wlbga ball type description
document no. 002-14797 rev. *h page 83 of 128 cyw4343x wlan gpio interface wrf_gpaio_out 67 o test pin. not connected in normal operation. clocks wrf_xtal_xon 75 o xtal oscillator output wrf_xtal_xop 74 i xtal oscillator input clk_req 153 o external system clock request?used when the system clock is not provided by a dedi cated crystal (for example, when a shared tcxo is used). asserted to indicate to the host that the clock is required. shared by bt, and wlan. lpo_in 76 i external sleep clock input (32.768 khz). if an external 32.768 khz clock cannot be provided, pull this pin low. however, ble will be always on and cannot go to deep sleep. fm fm_dac_vout1 37 o fm dac output 1 fm_dac_vout2 40 o fm dac output 2 fm_rfinmain 49 i fm rf input bluetooth pcm bt_pcm_clk or bt_i2s_clk 3 i/o pcm or i 2 s clock; can be master (output) or slave (input) bt_pcm_in or bt_i2s_di 20 i pcm or i 2 s data input sensing bt_pcm_out or bt_i2s_do 19 o pcm or i 2 s data output bt_pcmm_sync or bt_i2s_ws 17 i/o pcm sync or i2s ws; can be master (output) or slave (input) bluetooth gpio bt_agpio 52 i/o bluetooth analog gpio bt_gpio_2 13 i/o bluetooth general purpose i/o bt_gpio_3 5 i/o wpt_intb to wireless charging pmu. bt_gpio_4 8 i/o bsc_sda to/from wireless charging pmu. bt_gpio_5 10 i/o bsc_scl from wireless charging pmu bt_tm1 4 i/o arm jtag mode bluetooth uart and wake bt_uart_cts_n 22 i uart clear-to-send. ac tive-low clear-to-send signal for the hci uart interface. bt_uart_rts_n 7 o uart request-to-send. active-low request-to-send signal for the hci uart interface. bt_uart_rxd 1 i uart serial input. se rial data input for the hci uart interface. bt_uart_txd 12 o uart serial output. serial data output for the hci uart interface. bt_dev_wake 6 i/o dev_wake or general-purpose i/o signal bt_host_wake 11 i/o host_wake or general-purpose i/o signal note: by default, the bluetooth bt wake signals provide gpio/wake functi onality, and the uart pins provide uart functionality. through software configuration, the pcm interface can also be routed over the bt_wake/uart signals as follows: ? pcm_clk on the uart_rts_n pin ? pcm_out on the uart_cts_n pin ? pcm_sync on the bt_host_wake pin ? pcm_in on the bt_dev_wake pin in this case, the bt hci transport included sleep signaling will oper ate using uart_rxd and uart_txd; that is, using a 3-wire u art transport. table 23. wlcsp signal descriptions (cont.) signal name wlcsp bump type description or instruction
document no. 002-14797 rev. *h page 84 of 128 cyw4343x bluetooth/fm i 2 s bt_i2s_clk or bt_pcm_clk 15 i/o i 2 s or pcm clock; can be master (output) or slave (input) bt_i2s_di or bt_pcm_in 23 i i 2 s or pcm data input bt_i2s_do or bt_pcm_out 24 o i 2 s or pcm data output bt_i2s_ws or bt_pcm_sync 18 i/o i 2 s ws or pcm sync; can be master (output) or slave (input) miscellaneous wl_reg_on 148 i used by pmu to power up or power down the internal regulators used by the wlan section. also, when deasserted, this pin holds the wlan section in reset. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. bt_reg_on 149 i used by pmu to power up or power down the internal regulators used by the bluetooth/fm section. also, when deasserted, this pin holds the bluetooth/fm section in reset. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. wpt_3p3 146 n/a not used. do not connect to this pin. wpt_1p8 145 n/a not used. do not connect to this pin. gpio_0 100 i/o programmable gpio pin. this pin becomes an output pin when it is used as wlan_host_wake/out-of-band signal. gpio_1 101 i/o programmable gpio pin gpio_2 97 i/o programmable gpio pin gpio_3 98 i/o programmable gpio pin gpio_4 91 i/o programmable gpio pin gpio_5 94 i/o programmable gpio pin gpio_6 89 i/o programmable gpio pin gpio_7 87 i/o programmable gpio pin gpio_8 84 i/o programmable gpio pin gpio_9 82 i/o programmable gpio pin gpio_10 83 i/o programmable gpio pin gpio_11 81 i/o programmable gpio pin gpio_12 80 i/o programmable gpio pin gpio_13 119 i/o programmable gpio pin gpio_14 105 i/o programmable gpio pin gpio_15 109 i/o programmable gpio pin packageoption_0 110 i vddio packageoption_1 113 i ground packageoption_2 116 i ground jtag_sel 117 i jtag select. connect to ground. integrated voltage regulators sr_vddbat5v 129, 130, 132 i sr vbat input power supply sr_vlx 126, 127, 128 o cbuck switching regulator output. see table 42 on page 107 for details of the inducto r and capacitor required on this output. ldo_vddbat5v 141, 147 i ldo vbat ldo_vdd1p5 133, 135 i lnldo input vout_lnldo 138 o output of low-noise ldo (lnldo) vout_cldo 134, 136 o output of core ldo table 23. wlcsp signal descriptions (cont.) signal name wlcsp bump type description or instruction
document no. 002-14797 rev. *h page 85 of 128 cyw4343x bluetooth power supplies bt_ifvdd1p2 51 pwr bluetooth if-block power supply bt_lnavdd1p2 54 pwr bluetooth rf lna power supply bt_pavdd2p5 53 pwr bluetooth rf pa power supply bt_pllvdd1p2 59 pwr bluetooth rf pll power supply bt_vcovdd1p2 57 pwr bluetooth rf power supply bt_vddc 14, 16, 26, 28, 31, 34 pwr bluetooth core power supply bt_vddc_iso_1 9 pwr bluetooth core power supply bt_vddc_iso_2 2 pwr bluetooth core power supply power supplies fm_dac_avdd 41 pwr fm dac power supply fm_ifdvdd1p2 48 pwr fm if power supply fm_plldvdd1p2 43 pwr fm pll power supply fm_rfvdd1p2 45 pwr fm rf power supply fm_vcovdd1p2 44 pwr fm vco power supply pll_vddc 152 pwr core pll power supply sys_vddio 140 i vddio input supply. connect to vddio. vddc 86, 93, 95, 107, 114 i core supply for wlan and bt vout_3p3 139, 144 o 3.3v output supply. s ee the reference schematic for details. vout_3p3_sense 143 o voltage sense pin for ldo 3.3v output wcc_vddio 77, 79, 99, 103, 120, 137 i vddio input supply. connect to vddio. wl_vddm_iso 150 ? test pin. not connected in normal operation. wl_vddp_iso 96 ? test pin. not connected in normal operation. wrf_xtal_vdd1p2 73 i xtal oscillator supply wrf_pa_vdd3p3 70, 71 i power amplifier supply wrf_pmu_vdd1p35 68 i lnldo input supply table 23. wlcsp signal descriptions (cont.) signal name wlcsp bump type description or instruction
document no. 002-14797 rev. *h page 86 of 128 cyw4343x 14.9 wlan gpio signals and strapping options the pins listed in ta b l e 2 4 are sampled at power-on reset (por) to determine the various operating modes. sampling occurs a few milliseconds after an internal por or deassertion of the external por. after the por, each pin assumes the gpio or alternative function specified in the signal descripti ons table. each strapping option pin has an internal pull-up (pu) or pull-down (pd) r esistor that determines the default mode. to change the mode, connect an external pu re sistor to vddio or a pd resistor to ground using a 10 k ? resistor or less. note: refer to the reference board schematics for more information. 14.10 chip debug options the chip can be accessed for debugging via the jtag interface, multiplexed on the sdio_data_0 through sdio_data_3 (and sdio_clk) i/o or the bluetooth pcm i/o dependi ng on the bootstrap state of gpio_1 and gpio_2. ta b l e 2 5 shows the debug options of the device. ground bt_dvss 50 gnd bluetooth digital ground bt_lnavss 55 gnd bluetooth lna ground bt_pavss 35 gnd bluetooth pa ground bt_pllvss 56 gnd bluetooth pll ground bt_vcovss 58 gnd bluetooth vco ground fm_dac_avss 38 gnd fm dac analog ground fm_ifvss 47 gnd fm if-block ground fm_pllavss 39 gnd fm pll analog ground fm_rfvss 46 gnd fm rf ground fm_vcovss 42 gnd fm vco ground pll_vssc 151 gnd pll core ground pmu_avss 131 i quiet ground sr_pvss 123, 124 i switcher-power ground vssc 21, 25, 27, 29, 30, 32, 33, 36, 78, 85, 88, 90, 92, 102, 106, 111, 121, 125, 142 i core ground for wlan and bt wrf_afe_gnd 60 i afe ground wrf_rx2g_gnd 62 i 2.4 ghz internal lna ground wrf_general_gnd 64 i miscellaneous rf ground wrf_pa_gnd3p3 65, 69 i 2.4 ghz pa ground wrf_vco_gnd 66 i vco/lo generator ground wrf_xtal_gnd1p2 72 i xtal ground table 24. gpio functions and strapping options pin name wlbga pin # default function description sdio_data_2 l7 1 wlan host interface select this pin selects the wlan host interface mode. the default is sdio. for gspi, pull this pin low. table 25. chip debug options jtag_sel gpio_2 gpio_1 function sdio i/o pad function bt pcm i/o pad function 0 0 0 normal mode sdio bt pcm 0 0 1 jtag over sdio jtag bt pcm table 23. wlcsp signal descriptions (cont.) signal name wlcsp bump type description or instruction
document no. 002-14797 rev. *h page 87 of 128 cyw4343x 14.11 i/o states the following notations are used in table 26 on page 87 : i: input signal o: output signal i/o: input/output signal pu = pulled up pd = pulled down nopull = neither pulled up nor pulled down 0 1 0 jtag over bt pcm sdio jtag 0 1 1 swd over gpio_1/ gpio_2 sdio bt pcm table 26. i/o states a name i/o keeper b active mode low power state/sleep (all power present) power-down c wl_reg_on = 0 bt_reg_on = 0 out-of-reset; (wl_reg_on = 1; bt_reg_on = do not care) (wl_reg_on = 1 bt_reg_on = 0) vddios present out-of-reset; (wl_reg_on = 0 bt_reg_on = 1) vddios present power rail wl_reg_on i n input; pd (pull-down can be disabled) input; pd (pull-down can be disabled) input; pd (of 200k) input; pd (200k) input; pd (200k) ? ? bt_reg_on i n input; pd (pull down can be disabled) input; pd (pull down can be disabled) input; pd (of 200k) input; pd (200k) input; pd (200k) input; pd (200k) ? clk_req i/o y open drain or push-pull (programmable). active high. open drain or push-pull (programmable). active high pd open drain, active high. open drain, active high. open drain, active high. wcc_vddio bt_host_ wake i/o y i/o; pu, pd, nopull (programmable) i/o; pu, pd, nopull (programmable) high-z, nopull ? input, pd output, drive low wcc_vddio bt_dev_wake i/o y i/o; pu, pd, nopull (programmable) input; pu, pd, nopull (programmable) high-z, nopull ? input, pd input, pd wcc_vddio bt_uart_cts i y input; nopull input; nopull high-z, nopull ? input; pu input, nopull wcc_vddio bt_uart_rts o y output; nopull output; nopull high-z, nopull ? input; pu output, nopull wcc_vddio bt_uart_rxd i y input; pu input; nopull high-z, nopull ? input; pu input, nopull wcc_vddio bt_uart_txd o y output; nopull output; nopull high-z, nopull ? input; pu output, nopull wcc_vddio sdio_data_0 i/o n sdio mode -> nopull sdio mode -> nopull sdio mode -> nopull sdio mode -> pu sdio mode -> nopull input; pu wcc_vddio sdio_data_1 i/o n sdio mode -> nopull sdio mode -> nopull sdio mode -> nopull sdio mode -> pu sdio mode -> nopull input; pu wcc_vddio table 25. chip debug options (cont.) jtag_sel gpio_2 gpio_1 function sdio i/o pad function bt pcm i/o pad function
document no. 002-14797 rev. *h page 88 of 128 cyw4343x sdio_data_2 i/o n sdio mode -> nopull sdio mode -> nopull sdio mode -> nopull sdio mode -> pu sdio mode -> nopull input; pu wcc_vddio sdio_data_3 i/o n sdio mode -> nopull sdio mode -> nopull sdio mode -> nopull sdio mode -> pu sdio mode -> nopull input; pu wcc_vddio sdio_cmd i/o n sdio mode -> nopull sdio mode -> nopull sd io mode -> nopull sdio mode -> pu sdio mode -> nopull input; pu wcc_vddio sdio_clk i n sdio mode -> nopull sdio mode -> nopull sdio mode -> nopull sdio mode -> nopull sdio mode -> nopull input wcc_vddio bt_pcm_clk i/o y input; nopull d input; nopull d high-z, nopull ? input, pd input, pd wcc_vddio bt_pcm_in i/o y input; nopull d input; nopull d high-z, nopull ? input, pd input, pd wcc_vddio bt_pcm_out i/o y input; nopull d input; nopull d high-z, nopull ? input, pd input, pd wcc_vddio bt_pcm_sync i/o y input; nopull d input; nopull d high-z, nopull ? input, pd input, pd wcc_vddio bt_i2s_ws i/o y input; nopull e input; nopull e high-z, nopull ? input, pd input, pd wcc_vddio bt_i2s_clk ] i/o y input; nopull e input; nopull e high-z, nopull ? input, pd output, drive low wcc_vddio bt_i2s_do [ i/o y input; nopull e input; nopull e high-z, nopull ? input, pd input, pd wcc_vddio jtag_sel i y pd pd high-z, nopull input, pd pd input, pd wcc_vddio gpio_0 i/o y tbd active mode high-z, nopull f input, sdio oob int, nopull active mode input, nopull wcc_vddio gpio_1 i/o y tbd active mode high-z, nopull f input, pd active mode input, strap, pd wcc_vddio gpio_2 i/o y tbd active mode high-z, nopull f input, gci gpio[7], nopull active mode input, strap, nopull wcc_vddio gpio_3 i/o y tbd active mode high-z, nopull f input, gci gpio[0], pu active mode input, pu wcc_vddio gpio_4 i/o y tbd active mode high-z, nopull f input, gci gpio[1], pu active mode input, pu wcc_vddio gpio_5 i/o n tbd active mode high-z, nopull f input, gci gpio[2], pu active mode input, pu wcc_vddio gpio_6 i/o y tbd active mode high-z, nopull f input, gci gpio[3], nopull active mode input, nopull wcc_vddio gpio_7 i/o y tbd active mode high-z, nopull f output, wlan uart rts#, nopull active mode output, nopull, low wcc_vddio gpio_8 i/o y tbd active mode high-z, nopull f input, wlan uart cts#, nopull active mode input, nopull wcc_vddio table 26. i/o states a (cont.) name i/o keeper b active mode low power state/sleep (all power present) power-down c wl_reg_on = 0 bt_reg_on = 0 out-of-reset; (wl_reg_on = 1; bt_reg_on = do not care) (wl_reg_on = 1 bt_reg_on = 0) vddios present out-of-reset; (wl_reg_on = 0 bt_reg_on = 1) vddios present power rail
document no. 002-14797 rev. *h page 89 of 128 cyw4343x gpio_9 i/o y tbd active mode high-z, nopull f input, wlan uart rx, nopull active mode input, nopull wcc_vddio gpio_10 i/o y tbd active mode high-z, nopull f output, wlan uart tx, nopull active mode output, nopull, low wcc_vddio gpio_11 i/o y tbd active mode high-z, nopull f input, low, nopull active mode input, nopull wcc_vddio gpio_12 i/o y tbd active mode high-z, nopull f input, gci gpio[6], nopull active mode input, nopull wcc_vddio gpio_13 i/o y tbd active mode high-z, nopull f input, gci gpio[7], nopull active mode input, nopull wcc_vddio gpio_14 i/o y tbd active mode high-z, nopull f input, pd active mode input, pd wcc_vddio gpio_15 i/o y tbd active mode high-z, nopull f input, pd active mode input, pd wcc_vddio a. pu = pulled up, pd = pulled down. b. n = pad has no keeper. y = pad has a keeper. keeper is always acti ve except in the power-down state. if there is no keeper, a nd it is an input and there is nopull, then the pad should be driven to prevent leakage due to floating pad, for example, sdio_clk. c. in the power-down state (xx_reg_on = 0): high-z; no pull => the pad is disabled because power is not supplied. d. depending on whether the pcm interface is enabled and the configur ation is master or slave mode, it can be either an output o r input. e. depending on whether the i 2 s interface is enabled and the configuration is master or slave mode, it can be either an output or input. f. the gpio pull states for the active and low-power states are ha rdware defaults. they can all be subsequently programmed as a pull-up or pull-down. table 26. i/o states a (cont.) name i/o keeper b active mode low power state/sleep (all power present) power-down c wl_reg_on = 0 bt_reg_on = 0 out-of-reset; (wl_reg_on = 1; bt_reg_on = do not care) (wl_reg_on = 1 bt_reg_on = 0) vddios present out-of-reset; (wl_reg_on = 0 bt_reg_on = 1) vddios present power rail
document no. 002-14797 rev. *h page 90 of 128 cyw4343x 15. dc characteristics note: values in this data sheet are design goals and are subject to change based on the results of device characterization. 15.1 absolute maximum ratings caution! the absolute maximum ratings in ta b l e 2 7 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. functional oper ation is not guaranteed under t hese conditions. excluding vbat, operation at the absolute maximum conditions for extended periods can adversely affect long-term reliability of the device. 15.2 environmental ratings the environmental ratings are shown in ta b l e 2 8 . 15.3 electrostatic discharge specifications extreme caution must be exercised to prevent electrostatic discharge (esd) damage. proper use of wrist and heel grounding strap s to discharge static electricity is required when handling these devices. always store unused material in its antistatic packagi ng. table 27. absolute maximum ratings rating symbol value unit dc supply for vbat and pa driver supply vbat ?0.5 to +6.0 a a. continuous operation at 6.0v is supported. v dc supply voltage for digital i/o vddio ?0.5 to 3.9 v dc supply voltage for rf switch i/os vddio_rf ?0.5 to 3.9 v dc input supply voltage for cldo and lnldo ? ?0.5 to 1.575 v dc supply voltage for rf analog vddrf ?0.5 to 1.32 v dc supply voltage for core vddc ?0.5 to 1.32 v maximum undershoot voltage for i/o b b. duration not to exceed 25% of the duty cycle. v undershoot ?0.5 v maximum overshoot voltage for i/o b v overshoot vddio + 0.5 v maximum junction temperature t j 125 c table 28. environmental ratings characteristic value units conditions/comments ambient temperature (t a ) ?30 to +70c a a. functionality is guaranteed, but specifications require derating at extreme temperatures (see the specification tables for de tails). ? c operation storage temperature ?40 to +125c ? c? relative humidity less than 60 % storage less than 85 % operation table 29. esd specifications pin type symbol condition esd rating unit esd, handling reference: nqy00083, section 3.4, group d9, table b esd_hand_hbm human body model contact discharge per jedec eid/jesd22-a114 1000 v machine model (mm) esd_hand_mm machine model contact 30 v cdm esd_hand_cdm charged device model contact discharge per jedec eia/jesd22-c101 300 v
document no. 002-14797 rev. *h page 91 of 128 cyw4343x 15.4 recommended operating conditions and dc characteristics functional operation is not guarant eed outside the limits shown in table 30 , and operation outside these limits for extended periods can adversely affect long-term reliability of the device. table 30. recommended operating conditions and dc characteristics element symbol value unit minimum typical maximum dc supply voltage for vbat vbat 3.0 a a. the cyw4343x is functional across this range of voltages. howeve r, optimal rf performance specified in the data sheet is guar anteed only for 3.2v < vbat < 4.8v. ? 4.8 b b. the maximum continuous voltage is 4.8v. voltages up to 6.0v for up to 10 seconds, cumulative duration over the lifetime of th e device are allowed. voltages as high as 5.0v for up to 250 seconds, cu mulative duration over the lifetime of the device are allowed. v dc supply voltage for core vdd 1.14 1.2 1.26 v dc supply voltage for rf blocks in chip vddrf 1.14 1.2 1.26 v dc supply voltage for digital i/o vddio, vddio_sd 1.71 ? 3.63 v dc supply voltage for rf switch i/os vddio_rf 3.13 3.3 3.46 v external tssi input tssi 0.15 ? 0.95 v internal por threshold vth_por 0.4 ? 0.7 v sdio interface i/o pins for vddio_sd = 1.8v: input high voltage vih 1.27 ? ?v input low voltage vil ? ?0.58v output high voltage @ 2 ma voh 1.40 ? ?v output low voltage @ 2 ma vol ? ?0.45v for vddio_sd = 3.3v: input high voltage vih 0.625 vddio ? ?v input low voltage vil ? ? 0.25 vddio v output high voltage @ 2 ma voh 0.75 vddio ?? v output low voltage @ 2 ma vol ? ? 0.125 vddio v other digital i/o pins for vddio = 1.8v: input high voltage vih 0.65 vddio ? ?v input low voltage vil ? ? 0.35 vddio v output high voltage @ 2 ma voh vddio ? 0.45 ? ?v output low voltage @ 2 ma vol ? ?0.45v for vddio = 3.3v: input high voltage vih 2.00 ? ?v input low voltage vil ? ?0.80v output high voltage @ 2 ma voh vddio ? 0.4 ? ?v output low voltage @ 2 ma vol ? ?0.40v rf switch control output pins c c. programmable 2 ma to 16 ma drive strength. default is 10 ma. for vddio_rf = 3.3v: output high voltage @ 2 ma voh vddio ? 0.4 ? ?v output low voltage @ 2 ma vol ? ?0.40v input capacitance c in ? ? 5 pf
document no. 002-14797 rev. *h page 92 of 128 cyw4343x 16. wlan rf specifications the cyw4343x includes an integrated direct conversion radio that supports the 2.4 ghz ba nd. this section describes the rf char- acteristics of the 2.4 ghz radio. note: values in this data sheet are design goals and may change based on device characterization results. unless otherwise stated, the specifications in this section apply when the operating c onditions are within the limits specified in table 28, ?environmental ratings,? on page 90 and table 30, ?recommended operating cond itions and dc characteristics,? on page 91 . functional operation outside these limits is not guaranteed. typical values apply for the following conditions: vbat = 3.6v. ambient temperature +25c. figure 50. rf port location note: all specifications appl y at the chip port unle ss otherwise specified. 16.1 2.4 ghz band general rf specifications 16.2 wlan 2.4 ghz receiver performance specifications note: unless otherwise specified, the specifications in table 32 are measured at the chip port (for the location of the chip port, see figure 50 on page 92 ). table 31. 2.4 ghz band general rf specifications item condition minimum typical maximum unit tx/rx switch time including tx ramp down ? ? 5 s rx/tx switch time including tx ramp up ? ? 2 s table 32. wlan 2.4 ghz receiver performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz rx sensitivity (8% per for 1024 octet psdu) a 1 mbps dsss ?97.5 ?99.5 ? dbm 2 mbps dsss ?93.5 ?95.5 ? dbm 5.5 mbps dsss ?91.5 ?93.5 ? dbm 11 mbps dsss ?88.5 ?90.5 ? dbm tx rx c2 10 pf l1 4.7 nh c1 10 pf filter chip port antenna port cyw4343x
document no. 002-14797 rev. *h page 93 of 128 cyw4343x rx sensitivity (10% per for 1000 octet psdu) at wlan rf port a 6 mbps ofdm ?91.5 ?93.5 ? dbm 9 mbps ofdm ?90.5 ?92.5 ? dbm 12 mbps ofdm ?87.5 ?89.5 ? dbm 18 mbps ofdm ?85.5 ?87.5 ? dbm 24 mbps ofdm ?82.5 ?84.5 ? dbm 36 mbps ofdm ?80.5 ?82.5 ? dbm 48 mbps ofdm ?76.5 ?78.5 ? dbm 54 mbps ofdm ?75.5 ?77.5 ? dbm rx sensitivity (10% per for 4096 octet psdu). defined for default parameters: mixed mode, 800 ns gi. 20 mhz channel spacing for all mcs rates (mixed mode) 256-qam, r = 5/6 ?67.5 ?69.5 ? dbm 256-qam, r = 3/4 ?69.5 ?71.5 ? dbm mcs7 ?71.5 ?73.5 ? dbm mcs6 ?73.5 ?75.5 ? dbm mcs5 ?74.5 ?76.5 ? dbm mcs4 ?79.5 ?81.5 ? dbm mcs3 ?82.5 ?84.5 ? dbm mcs2 ?84.5 ?86.5 ? dbm mcs1 ?86.5 ?88.5 ? dbm mcs0 ?90.5 ?92.5 ? dbm table 32. wlan 2.4 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit
document no. 002-14797 rev. *h page 94 of 128 cyw4343x blocking level for 3 db rx sensitivity degradation (without external filtering). b 704?716 mhz lte ? ?13 ? dbm 777?787 mhz lte ? ?13 ? dbm 776?794 mhz cdma2000 ? ?13.5 ? dbm 815?830 mhz lte ? ?12.5 ? dbm 816?824 mhz cdma2000 ? ?13.5 ? dbm 816?849 mhz lte ? ?11.5 ? dbm 824?849 mhz wcdma ? ?11.5 ? dbm 824?849 mhz cdma2000 ? ?12.5 ? dbm 824?849 mhz lte ? ?11.5 ? dbm 824?849 mhz gsm850 ? ?8 ? dbm 830?845 mhz lte ? ?11.5 ? dbm 832?862 mhz lte ? ?11.5 ? dbm 880?915 mhz wcdma ? ?10 ? dbm 880?915 mhz lte ? ?12 ? dbm 880?915 mhz e-gsm ? ?9 ? dbm 1710?1755 mhz wcdma ? ?13 ? dbm 1710?1755 mhz lte ? ?14.5 ? dbm 1710?1755 mhz cdma2000 ? ?14.5 ? dbm 1710?1785 mhz wcdma ? ?13 ? dbm 1710?1785 mhz lte ? ?14.5 ? dbm 1710?1785 mhz gsm1800 ? ?12.5 ? dbm 1850?1910 mhz gsm1900 ? ?11.5 ? dbm 1850?1910 mhz cdma2000 ? ?16 ? dbm 1850?1910 mhz wcdma ? ?13.5 ? dbm 1850?1910 mhz lte ? ?16 ? dbm 1850?1915 mhz lte ? ?17 ? dbm 1920?1980 mhz wcdma ? ?17.5 ? dbm 1920?1980 mhz cdma2000 ? ?19.5 ? dbm 1920?1980 mhz lte ? ?19.5 ? dbm 2300?2400 mhz lte ? ?44 ? dbm 2500?2570 mhz lte ? ?43 ? dbm 2570?2620 mhz lte ? ?34 ? dbm 5g wlan ? >?4 ? dbm maximum receive level @ 2.4 ghz @ 1, 2 mbps (8% per, 1024 octets) ?6 ? ? dbm @ 5.5, 11 mbps (8% per, 1024 octets) ?12 ? ? dbm @ 6?54 mbps (10% per, 1000 octets) ?15.5 ? ? dbm adjacent channel rejection-dsss. (difference between interfering and desired signal [25 mhz apart] at 8% per for 1024 octet psdu with desired signal level as specified in condition/notes.) 11 mbps dsss ?70 dbm 35 ? ? db table 32. wlan 2.4 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit
document no. 002-14797 rev. *h page 95 of 128 cyw4343x 16.3 wlan 2.4 ghz transmitte r performance sp ecifications note: unless otherwise specified, the specifications in table 32 are measured at the chip port (for the location of the chip port, see figure 50 on page 92 ). adjacent channel rejection-ofdm. (difference between interfering and desired signal (25 mhz apart) at 10% per for 1000 c octet psdu with desired signal level as specified in condition/notes.) 6 mbps ofdm ?79 dbm 16 ? ? db 9 mbps ofdm ?78 dbm 15 ? ? db 12 mbps ofdm ?76 dbm 13 ? ? db 18 mbps ofdm ?74 dbm 11 ? ? db 24 mbps ofdm ?71 dbm 8 ? ? db 36 mbps ofdm ?67 dbm 4 ? ? db 48 mbps ofdm ?63 dbm 0 ? ? db 54 mbps ofdm ?62 dbm ?1 ? ? db 65 mbps ofdm ?61 dbm ?2 ? ? db rcpi accuracy d range ?98 dbm to ?75 dbm ?3 ? 3 db range above ?75 dbm ?5 ? 5 db return loss zo = 50 ? across the dynamic range. 10 ? ? db a. optimal rf performance, as specified in this data sheet , is guaranteed only for temperatures between ?10c and 55c. b. the cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that b and for the purpose of this test. it is not intended to indicate any spec ific usage of each band in any specific country. c. for 65 mbps, the size is 4096. d. the minimum and maximum values shown have a 95% confidence level. table 33. wlan 2.4 ghz transmi tter performance specifications parameter condition/notes minimum typical maximum unit frequency range ? ? ? ? mhz transmitted power in cellular and wlan 5g bands (at 21 dbm, 90% duty cycle, 1 mbps cck). a 776?794 mhz cdma2000 ? ?167.5 ? dbm/hz 869?960 mhz cdmaone, gsm850 ? ?163.5 ? dbm/hz 1450?1495 mhz dab ? ?154.5 ? dbm/hz 1570?1580 mhz gps ? ?152.5 ? dbm/hz 1592?1610 mhz glonass ? ?149.5 ? dbm/hz 1710?1800 mhz dsc-1800-uplink ? ?145.5 ? dbm/hz 1805?1880 mhz gsm1800 ? ?143.5 ? dbm/hz 1850?1910 mhz gsm1900 ? ?140.5 ? dbm/hz 1910?1930 mhz tdscdma, lte ? ?138.5 ? dbm/hz 1930?1990 mhz gsm1900, cdmaone, wcdma ? ?139 ? dbm/hz 2010?2075 mhz tdscdma ? ?127.5 ? dbm/hz 2110?2170 mhz wcdma ? ?124.5 ? dbm/hz 2305?2370 mhz lte band 40 ? ?104.5 ? dbm/hz 2370?2400 mhz lte band 40 ? ?81.5 ? dbm/hz 2496?2530 mhz lte band 41 ? ?94.5 ? dbm/hz 2530?2560 mhz lte band 41 ? ?120.5 ? dbm/hz 2570?2690 mhz lte band 41 ? ?121.5 ? dbm/hz 5000?5900 mhz wlan 5g ? ?109.5 ? ? table 32. wlan 2.4 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit
document no. 002-14797 rev. *h page 96 of 128 cyw4343x 16.4 general spurious emissions specifications harmonic level (at 21 dbm with 90% duty cycle, 1 mbps cck) 4.8?5.0 ghz 2nd harmonic ? ?26.5 ? dbm/ mhz 7.2?7.5 ghz 3rd harmonic ? ?23.5 ? dbm/ mhz 9.6?10 ghz 4th harmonic ? ?32.5 ? dbm/ mhz tx power at the chip port for the highest power level setting at 25c, vba = 3.6v, and spectral mask and evm compliance b, c ? evm does not exceed ieee 802.11b (dsss/cck) ?9 db 21 ? ? dbm ofdm, bpsk ?8 db 20.5 ? ? dbm ofdm, qpsk ?13 db 20.5 ? ? dbm ofdm, 16-qam ?19 db 20.5 ? ? dbm ofdm, 64-qam (r = 3/4) ?25 db 18 ? ? dbm ofdm, 64-qam (r = 5/6) ?27 db 17.5 ? ? dbm ofdm, 256-qam (r = 5/6) ?32 db 15 ? ? dbm tx power control dynamic range ?9??db closed loop tx power variation at highest power level setting across full temperature and voltage range. applies across 5 to 21 dbm output power range. ??1.5db carrier suppression ? 15 ? ? dbc gain control step ? ? 0.25 ? db return loss zo = 50 4 6 ? db load pull variation for output power, evm, and adjacent channel power ratio (acpr) vswr = 2:1. evm degradation ? 3.5 ? db output power variation ? 2 ? db acpr-compliant power level ? 15 ? dbm vswr = 3:1. evm degradation ? 4 ? db output power variation ? 3 ? db acpr-compliant power level ? 15 ? dbm a. the cellular standards listed indicate onl y typical usages of that band in some countries. other standards may also be used w ithin those bands. b. tx power for channel 1 and channel 11 is specified separately by nonvolatile memory parameters to ensure band-edge compliance . c. optimal rf performance, as specified in this data sheet , is guaranteed only for temperatures between ?10c and 55c. table 34. general spurious emissions specifications parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz general spurious emissions tx emissions 30 mhz < f < 1 ghz rbw = 100 khz ? ?99 ?96 dbm 1 ghz < f < 12.75 ghz rbw = 1 mhz ? ?44 ?41 dbm 1.8 ghz < f < 1.9 ghz rbw = 1 mhz ? ?68 ?65 dbm 5.15 ghz < f < 5.3 ghz rbw = 1 mhz ? ?88 ?85 dbm rx/standby emissions 30 mhz < f < 1 ghz rbw = 100 khz ? ?99 ?96 dbm 1 ghz < f < 12.75 ghz rbw = 1 mhz ? ?54 ?51 dbm 1.8 ghz < f < 1.9 ghz rbw = 1 mhz ? ?88 ?85 dbm 5.15 ghz < f < 5.3 ghz rbw = 1 mhz ? ?88 ?85 dbm note: the specifications in this table apply at the chip port. table 33. wlan 2.4 ghz transmitter performance specifications (cont.) parameter condition/notes minimum typical maximum unit
document no. 002-14797 rev. *h page 97 of 128 cyw4343x 17. bluetooth rf specifications note: values in this data sheet are design goals and are subject to change based on the results of device characterization. unless otherwise stated, limit values apply for the conditions sp ecified in table 28, ?environ mental ratings,? on page 90 and table 30, ?recommended operating conditions and dc characteri stics,? on page 91. typical values apply for the following condi- tions: vbat = 3.6v. ambient temperature +25c. note: all bluetooth specifications appl y at the chip port. for the location of the chip port, see figure 50: ?rf port location,? on page 92 . table 35. bluetooth receiver rf specifications parameter conditions minimum typical maximum unit note: the specifications in this tabl e are measured at the chip output port unless otherwise specified. general frequency range ? 2402 ? 2480 mhz rx sensitivity gfsk, 0.1% ber, 1 mbps ? ?94 ? dbm ? /4?dqpsk, 0.01% ber, 2 mbps ? ?96 ? dbm 8?dpsk, 0.01% ber, 3 mbps ? ?90 ? dbm input ip3 ? ?16 ? ? dbm maximum input at antenna ? ? ? ?20 dbm interference performance a c/i co-channel gfsk, 0.1% ber ? ? 11 db c/i 1 mhz adjacent channel gfsk, 0.1% ber ? ? 0.0 db c/i 2 mhz adjacent channel gfsk, 0.1% ber ? ? ?30 db c/i ? 3 mhz adjacent channel gfsk, 0.1% ber ? ? ?40 db c/i image channel gfsk, 0.1% ber ? ? ?9 db c/i 1 mhz adjacent to image channel gfsk, 0.1% ber ? ? ?20 db c/i co-channel ? /4?dqpsk, 0.1% ber ? ? 13 db c/i 1 mhz adjacent channel ? /4?dqpsk, 0.1% ber ? ? 0.0 db c/i 2 mhz adjacent channel ? /4?dqpsk, 0.1% ber ? ? ?30 db c/i ? 3 mhz adjacent channel ? /4?dqpsk, 0.1% ber ? ? ?40 db c/i image channel ? /4?dqpsk, 0.1% ber ? ? ?7 db c/i 1 mhz adjacent to image channel ? /4?dqpsk, 0.1% ber ? ? ?20 db c/i co-channel 8?dpsk, 0.1% ber ? ? 21 db c/i 1 mhz adjacent channel 8?dpsk, 0.1% ber ? ? 5.0 db c/i 2 mhz adjacent channel 8?dpsk, 0.1% ber ? ? ?25 db c/i ? 3 mhz adjacent channel 8?dpsk, 0.1% ber ? ? ?33 db c/i image channel 8?dpsk, 0.1% ber ? ? 0.0 db c/i 1 mhz adjacent to image channel 8?dpsk, 0.1% ber ? ? ?13 db out-of-band blocking performance (cw) 30?2000 mhz 0.1% ber ? ?10.0 ? dbm 2000?2399 mhz 0.1% ber ? ?27 ? dbm 2498?3000 mhz 0.1% ber ? ?27 ? dbm 3000 mhz?12.75 ghz 0.1% ber ? ?10.0 ? dbm
document no. 002-14797 rev. *h page 98 of 128 cyw4343x out-of-band blocking performance, modulated interferer (lte) gfsk (1 mbps) 2310 mhz lte band40 tdd 20m bw ? ?20 ? dbm 2330 mhz lte band40 tdd 20m bw ? ?19 ? dbm 2350 mhz lte band40 tdd 20m bw ? ?20 ? dbm 2370 mhz lte band40 tdd 20m bw ? ?24 ? dbm 2510 mhz lte band7 fdd 20m bw ? ?24 ? dbm 2530 mhz lte band7 fdd 20m bw ? ?21 ? dbm 2550 mhz lte band7 fdd 20m bw ? ?21 ? dbm 2570 mhz lte band7 fdd 20m bw ? ?20 ? dbm ? /4 dpsk (2 mbps) 2310 mhz lte band40 tdd 20m bw ? ?20 ? dbm 2330 mhz lte band40 tdd 20m bw ? ?19 ? dbm 2350 mhz lte band40 tdd 20m bw ? ?20 ? dbm 2370 mhz lte band40 tdd 20m bw ? ?24 ? dbm 2510 mhz lte band7 fdd 20m bw ? ?24 ? dbm 2530 mhz lte band7 fdd 20m bw ? ?20 ? dbm 2550 mhz lte band7 fdd 20m bw ? ?20 ? dbm 2570 mhz lte band7 fdd 20m bw ? ?20 ? dbm 8dpsk (3 mbps) 2310 mhz lte band40 tdd 20m bw ? ?20 ? dbm 2330 mhz lte band40 tdd 20m bw ? ?19 ? dbm 2350 mhz lte band40 tdd 20m bw ? ?20 ? dbm 2370 mhz lte band40 tdd 20m bw ? ?24 ? dbm 2510 mhz lte band7 fdd 20m bw ? ?24 ? dbm 2530 mhz lte band7 fdd 20m bw ? ?21 ? dbm 2550 mhz lte band7 fdd 20m bw ? ?20 ? dbm 2570 mhz lte band7 fdd 20m bw ? ?20 ? dbm out-of-band blocking performance, modulated interf erer (non-lte) gfsk (1 mbps) a 698?716 mhz wcdma ? ?12 ? dbm 776?849 mhz wcdma ? ?12 ? dbm 824?849 mhz gsm850 ? ?12 ? dbm 824?849 mhz wcdma ? ?11 ?dbm 880?915 mhz e-gsm ? ?11 ? dbm 880?915 mhz wcdma ? ?16 ? dbm 1710?1785 mhz gsm1800 ? ?15 ? dbm 1710?1785 mhz wcdma ? ?18 ? dbm 1850?1910 mhz gsm1900 ? ?20 ? dbm table 35. bluetooth receiver rf specifications (cont.) parameter conditions minimum typical maximum unit
document no. 002-14797 rev. *h page 99 of 128 cyw4343x 1850?1910 mhz wcdma ? ?17 ? dbm 1880?1920 mhz td-scdma ? ?18 ? dbm 1920?1980 mhz wcdma ? ?18 ? dbm 2010?2025 mhz td?scdma ? ?18 ? dbm 2500?2570 mhz wcdma ? ?21 ? dbm ? /4 dpsk (2 mbps) a 698?716 mhz wcdma ? ?8 ? dbm 776?794 mhz wcdma ? ?8 ? dbm 824?849 mhz gsm850 ? ?9 ? dbm 824?849 mhz wcdma ? ?9 ? dbm 880?915 mhz e-gsm ? ?8 ? dbm 880?915 mhz wcdma ? ?8 ? dbm 1710?1785 mhz gsm1800 ? ?14 ? dbm 1710?1785 mhz wcdma ? ?14 ? dbm 1850?1910 mhz gsm1900 ? ?15 ? dbm 1850?1910 mhz wcdma ? ?14 ? dbm 1880?1920 mhz td-scdma ? ?16 ? dbm 1920?1980 mhz wcdma ? ?15 ? dbm 2010?2025 mhz td-scdma ? ?17 ? dbm 2500?2570 mhz wcdma ? ?21 ? dbm 8dpsk (3 mbps) a 698?716 mhz wcdma ? ?11 ? dbm 776?794 mhz wcdma ? ?11 ? dbm 824?849 mhz gsm850 ? ?11 ? dbm 824?849 mhz wcdma ? ?12 ? dbm 880?915 mhz e-gsm ? ?11 ? dbm 880?915 mhz wcdma ? ?11 ? dbm 1710?1785 mhz gsm1800 ? ?16 ? dbm 1710?1785 mhz wcdma ? ?15 ? dbm 1850?1910 mhz gsm1900 ? ?17 ? dbm 1850?1910 mhz wcdma ? ?17 ? dbm 1880?1920 mhz td-scdma ? ?17 ? dbm 1920?1980 mhz wcdma ? ?17 ? dbm 2010?2025 mhz td-scdma ? ?18 ? dbm 2500?2570 mhz wcdma ? ?21 ? dbm rx lo leakage 2.4 ghz band ? ? ?90.0 ?80.0 dbm spurious emissions 30 mhz?1 ghz ? ?95 ?62 dbm 1?12.75 ghz ? ?70 ?47 dbm 869?894 mhz ? ?147 ? dbm/hz 925?960 mhz ? ?147 ? dbm/hz 1805?1880 mhz ? ?147 ? dbm/hz 1930?1990 mhz ? ?147 ? dbm/hz table 35. bluetooth receiver rf specifications (cont.) parameter conditions minimum typical maximum unit
document no. 002-14797 rev. *h page 100 of 128 cyw4343x 2110?2170 mhz ? ?147 ? dbm/hz a. the bluetooth reference level for the required signal at the bluetooth chip port is 3 db higher than the typical sensitivity l evel. table 36. lte specifications for spurious emissions parameter conditions typical unit 2500?2570 mhz band 7 ?147 dbm/hz 2300?2400 mhz band 40 ?147 dbm/hz 2570?2620 mhz band 38 ?147 dbm/hz 2545?2575 mhz xgp band ?147 dbm/hz table 35. bluetooth receiver rf specifications (cont.) parameter conditions minimum typical maximum unit
document no. 002-14797 rev. *h page 101 of 128 cyw4343x table 37. bluetooth transmitter rf specifications a a. unless otherwise specified, the specifications in this table ap ply at the chip output port, and output power specifications a re with the temperature correction algorithm and tssi enabled. parameter conditions minimum typical maximum unit general frequency range 2402 ? 2480 mhz basic rate (gfsk) tx power at bluetooth ? 12.0 ? dbm qpsk tx power at bluetooth ? 8.0 ? dbm 8psk tx power at bluetooth ? 8.0 ? dbm power control step ? 2 4 8 db gfsk in-band spur ious emissions ?20 dbc bw ? ? 0.93 1 mhz edr in-band spur ious emissions 1.0 mhz < |m ? n| < 1.5 mhz m ? n = the frequency range for which the spurious emission is measured relative to the transmit center frequency. ? ?38 ?26.0 dbc 1.5 mhz < |m ? n| < 2.5 mhz ? ?31 ?20.0 dbm |m ? n| ? 2.5 mhz b b. typically measured at an offset of 3 mhz. ? ?43 ?40.0 dbm out-of-band spurious emissions 30 mhz to 1 ghz ? ? ? ?36.0 c,d c. the maximum value represents the value required for bluetoot h qualification as defined in the v4.1 specification. d. the spurious emissions during idle mode are the same as specified in table 37 on page 101 . dbm 1 ghz to 12.75 ghz ? ? ? ?30.0 d,e,f e. specified at the bluetooth antenna port. f. meets this specification using a front-end band-pass filter. dbm 1.8 ghz to 1.9 ghz ? ? ? ?47.0 dbm 5.15 ghz to 5.3 ghz ? ? ? ?47.0 dbm gps band spurio us emissions spurious emissions ? ? ?103 ? dbm out-of-band no ise floor g g. transmitted power in cellular and fm bands at the bluetooth antenna port. see figure 50 on page 92 for location of the port. 65?108 mhz fm rx ? ?147 ? dbm/hz 776?794 mhz cdma2000 ? ?146 ? dbm/hz 869?960 mhz cdmaone, gsm850 ? ?146 ? dbm/hz 925?960 mhz e-gsm ? ?146 ? dbm/hz 1570?1580 mhz gps ? ?146 ? dbm/hz 1805?1880 mhz gsm1800 ? ?144 ? dbm/hz 1930?1990 mhz gsm1900, cdmaone, wcdma ? ?143 ? dbm/hz 2110?2170 mhz wcdma ? ?137 ? dbm/hz table 38. lte specifications for out-of-band noise floor parameter conditions typical unit 2500?2570 mhz band 7 ?130 dbm/hz 2300?2400 mhz band 40 ?130 dbm/hz 2570?2620 mhz band 38 ?130 dbm/hz
document no. 002-14797 rev. *h page 102 of 128 cyw4343x 2545?2575 mhz xgp band ?130 dbm/hz table 39. local oscillator performance parameter minimum typical maximum unit lo performance lock time ? 72 ? ? s initial carrier frequency tolerance ? 25 75 khz frequency drift dh1 packet ? 8 25 khz dh3 packet ? 8 40 khz dh5 packet ? 8 40 khz drift rate ? 5 20 khz/50 s frequency deviation 00001111 sequence in payload a a. this pattern represents an average deviation in payload. 140 155 175 khz 10101010 sequence in payload b b. pattern represents the maximum deviation in payload for 99.9% of all frequency deviations. 115 140 ? khz channel spacing ?1?mhz table 40. ble rf specifications parameter conditions minimum typical maximum unit frequency range ? 2402 ? 2480 mhz rx sense a a. the bluetooth tester is set so that dirty tx is on. gfsk, 0.1% ber, 1 mbps ? ?97 ? dbm tx power b b. ble tx power can be increased to compensate for front-end losses such as bpf, diplexer, switch, etc.). the output is capped a t 12 dbm. the ble tx power at the antenna port cannot exceed the 10 dbm specification limit. ? ? 8.5 ? dbm mod char: delta f1 average ? 225 255 275 khz mod char: delta f2 max c c. at least 99.9% of all delta f2 max. frequency values recorded over 10 packets must be greater than 185 khz. ?99.9??% mod char: ratio ? 0.8 0.95 ? % table 38. lte specifications fo r out-of-band noi se floor (cont.) parameter conditions typical unit
document no. 002-14797 rev. *h page 103 of 128 cyw4343x 18. fm receiver specifications note: values in this data sheet are design goals and are subject to change based on the results of device characterization. unless otherwise stated, limit values apply for the conditions specified in table 28, ?environmental ratings,? on page 90 and table 30, ?recommended operating conditi ons and dc characteristics,? on page 91 . typical values apply for the following condi- tions: vbat = 3.6v. ambient temperature +25c. table 41. fm receiver specifications parameter conditions a minimum typical maximum units rf parameters operating frequency b frequencies inclusive 65 ? 108 mhz sensitivity c fm only, snr 26 db ? 1 ? dbv emf ? 1.1 ? v emf ??5? dbv receiver adjacent channel selectivity c,d measured for 30 db snr at audio output. signal of interest: 23 dbv emf (14.1 v emf). at 200 khz. ? 51 ? db at 400 khz. ? 62 ? db intermediate signal-plus- noise to noise ratio (s + n)/ n, stereo c vin = 20 dbv (10 v emf). 45 53 ? db intermodulation performance c,d blocker level increased until desired at 30 db snr. wanted signal: 33 dbv emf (45 v emf) modulated interferer: at f wanted + 400 khz and + 4mhz. cw interferer: at f wanted + 800 khz and + 8mhz. ?55? dbc am suppression, mono c vin = 23 dbv emf (14.1 v emf). am at 400 hz with m = 0.3. no a-weighted or any other filtering applied. 40 ? ? db rds rds sensitivity e,f rds deviation = 1.2 khz. ? 17 ? dbv emf ? 7.1 ? v emf ?11? dbv rds deviation = 2 khz. ? 13 ? dbv emf ? 4.4 ? v emf ?7? dbv rds selectivity f wanted signal: 33 dbv emf (45 v emf), 2 khz rds deviation. interferer: ? f = 40 khz, fmod = 1 khz. 200 khz ? 49 ? db 300 khz ? 52 ? db 400 khz ? 52 ? db rf input rf input impedance ? 1.5 ? ? k ? antenna tuning cap ? 2.5 ? 30 pf
document no. 002-14797 rev. *h page 104 of 128 cyw4343x maximum input level c snr > 26 db. ? ? 113 dbv emf ? ? 446 mv emf ? ? 107 dbv rf conducted emissions local oscillator breakthrough measured on the reference port. ? ? ?55 dbm 869?894 mhz, 925?960 mhz, 1805?1880 mhz, and 1930?1990 mhz. gps. ? ? ?90 dbm rf blocking levels at the fm antenna input with a 40 db snr (assumes a 50 ? input and excludes spurs) gsm850, e-gsm (standard); bw = 0.2 mhz. 824?849 mhz, 880?915 mhz. ?7? dbm gsm 850, e-gsm (edge); bw = 0.2 mhz. 824?849 mhz, 880?915 mhz. ?0? dbm gsm dcs 1800, pcs 1900 (standard, edge); bw = 0.2 mhz. 1710?1785 mhz, 1850?1910 mhz. ?12? dbm wcdma: ii (i), iii (iv,x); bw = 5 mhz. 1710?1785 mhz (1710?1755 mhz, 1710?1770 mhz), 1850?1980 mhz (1920?1980 mhz). ?12? dbm wcdma: v (vi), viii, xii, xiii, xiv; bw = 5 mhz. 824?849 mhz (830?840 mhz), 880?915 mhz. ?5? dbm cdma2000, cdma one; bw = 1.25 mhz. 776?794 mhz, 824?849 mhz, 887?925 mhz. ?0? dbm cdma2000, cdma one; bw= 1.25 mhz. 1750?1780 mhz, 1850?1910 mhz, 1920?1980 mhz. ?12? dbm bluetooth; bw = 1 mhz. 2402?2480 mhz. ?11? dbm lte, band 38, band 40, xgp band ? 11 ? dbm wlan-g/b; bw = 20 mhz. 2400?2483.5 mhz. ?11? dbm wlan-a; bw = 20 mhz. 4915?5825 mhz. ?6? dbm tuning frequency step ? 10 ? ? khz settling time single frequency switch in any direction to a frequency within the 88?108 mhz or 76?90 mhz bands. time measured to within 5 khz of the final frequency. ? 150 ? s search time total time for an automatic search to sweep from 88?108 mhz or 76?90 mhz (or in the reverse direction) assuming no channels are found. ??8 sec table 41. fm receiver specifications (cont.) parameter conditions a minimum typical maximum units
document no. 002-14797 rev. *h page 105 of 128 cyw4343x general audio audio output level g ? ?14.5 ? ?12.5 dbfs maximum audio output level h ???0dbfs dac audio output level conditions: vin = 66 dbv emf (2 mv emf), ? f = 22.5 khz, fmod = 1 khz, ? f pilot = 6.75 khz 72 ? 88 mv rms maximum dac audio output level h ? ? 333 ? mv rms audio dac output level difference i ??1?1db left and right ac mute fm input signal fully muted with dac enabled 60 ? ? db left and right hard mute fm input signal fully muted with dac disabled 80 ? ? db soft mute attenuation and start level muting is performed dynamically, proportional to the des ired fm input signal c/n. the muting characteristic is fully programmable. see audio features on page 57 . maximum signal plus noise- to-noise ratio (s + n)/n, mono i ??69?db maximum signal plus noise- to-noise ratio (s + n)/n, stereo g ??64?db total harmonic distortion, mono vin = 66 dbv emf(2 mv emf): ? ? ? ? ? f = 75 khz, fmod = 400 hz. ? ? 0.8 % ? f = 75 khz, fmod = 1 khz. ? ? 0.8 % ? f = 75 khz, fmod = 3 khz. ? ? 0.8 % ? f = 100 khz, fmod = 1 khz. ? ? 1.0 % total harmonic distortion, stereo vin = 66 dbv emf (2 mv emf), ? f = 67.5 khz, fmod = 1 khz, ? f pilot = 6.75 khz, l = r ??1.5% audio spurious products i range from 300 hz to 15 khz with respect to a 1 khz tone. ? ? ?60 dbc audio bandwidth, upper (? 3 db point) vin = 66 dbv emf (2 mv emf) ? f = 8 khz, for 50 s 15 ? ? khz audio bandwidth, lower (? 3 db point) ??20 hz audio in-band ripple 100 hz to 13 khz, vin = 66 dbv emf (2 mv emf), ? f = 8 khz, for 50 s. ?0.5 ? 0.5 db deemphasis time constant tolerance with respect to 50 and 75 s. ? ? 5 % rssi range with 1 db resolution and 5 db accuracy at room temperature. 3 ? 83 dbv emf 1.41 ? 1.41e+4 v emf ?3 ? 77 dbv stereo decoder stereo channel separation forced stereo mode vin = 66 dbv emf (2 mv emf), ? f = 67.5 khz, fmod = 1 khz, ? f pilot = 6.75 khz, r = 0, l = 1 ?44? db table 41. fm receiver specifications (cont.) parameter conditions a minimum typical maximum units
document no. 002-14797 rev. *h page 106 of 128 cyw4343x mono stereo blend and switching dynamically proportional to the desired fm input signal c/n. the blending and switching characteristics are fully programmable. see audio features on page 57 . pilot suppression vin = 66 dbv emf (2 mv emf), ? f = 75 khz, fmod = 1 khz. 46 ? ? db pause detection audio level at which a pause is detected relative to 1-khz tone, ? f = 22.5 khz. ? ? ? ? 4 values in 3 db steps ?21 ? ?12 db audio pause duration 4 values 20 ? 40 ms a. the following conditions are applied to all relevant tests un less otherwise indicated: preem phasis and deemphasis of 50 s, r = l for mono, baf = 300 hz to 15 khz, a-weighted filtering applied. b. contact your broadcom r epresentative for applicati ons operating between 65?76 mhz. c. signal of interest: ? f = 22.5 khz, fmod = 1 khz. d. interferer: ? f = 22.5 khz, fmod = 1 khz. e. rds sensitivity numbers are for 87.5?108 mhz only. f. vin = ? f = 32 khz, fmod = 1 khz, ? f pilot = 7.5 khz, and with an interferer for 95% of blocks decoded with no errors after correction, over a sample of 5000 blocks. g. vin = 66 dbv emf (2 mv emf), ? f = 22.5 khz, fmod = 1 khz, ? f pilot = 6.75 khz. h. vin = 66 dbv emf (2 mv emf), ? f = 100 khz, fmod = 1 khz, ? f pilot = 6.75 khz. i. vin = 66 dbv emf (2 mv emf), ? f = 22.5 khz, fmod = 1 khz. table 41. fm receiver specifications (cont.) parameter conditions a minimum typical maximum units
document no. 002-14797 rev. *h page 107 of 128 cyw4343x 19. internal regulator electrical specifications note: values in this data sheet are design goals and are subject to change based on device characterization results. functional operation is not guarant eed outside of the specification limits provided in this section. 19.1 core buck sw itching regulator 19.2 3.3v ldo (ldo3p3) table 42. core buck switching regulator (cbuck) specifications specification notes min. typ. max. units input supply voltage (dc) dc voltage r ange inclusive of disturbances. 2.4 3.6 4.8 a a. the maximum continuous voltage is 4.8v. voltages up to 6.0v for up to 10 seconds, cumulative duration, over the lifetime of t he device are allowed. voltages as high as 5.0v for up to 250 seconds, cumu lative duration, over the lifetime of the device are allowed. v pwm mode switching frequency ccm, load > 100 ma vbat = 3.6v. ? 4 ? mhz pwm output current ? ? ? 370 ma output current limit ? ? 1400 ? ma output voltage range programmable, 30 mv steps. default = 1.35v. 1.2 1.35 1.5 v pwm output voltage dc accuracy includes load and line regulation. forced pwm mode. ?4 ? 4 % pwm ripple voltage, static measur e with 20 mhz bandwidth limit. static load, max. ripple based on vbat = 3.6v, vout = 1.35v, fsw = 4 mhz, 2.2 h inductor l > 1.05 h, cap + board total-esr < 20 m ? , c out > 1.9 f, esl<200 ph ?720mvpp pwm mode peak efficiency peak efficiency at 200 ma load, inductor dcr = 200 m ? , vbat = 3.6v, vout = 1.35v ?85?% pfm mode efficiency 10 ma load current, inductor dcr = 200 m ? , vbat = 3.6v, vout = 1.35v ?77?% start-up time from power down vddio already on and steady. time from reg_on rising edge to cldo reaching 1.2v ? 400 500 s external inductor 0603 size, 2.2 h 20%, dcr = 0.2 ? 25% ?2.2?h external output capacitor ceramic, x5r, 0402, esr <30 m ? at 4 mhz, 4.7 f 20%, 10v 2.0 b b. minimum capacitor value refers to the re sidual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 4.7 10 c c. total capacitance includes those connec ted at the far end of the active load. f external input capacitor for sr_vddbatp5v pin, ceramic, x5r, 0603, esr < 30 m ? at 4 mhz, 4.7 f 20%, 10v 0.67 b 4.7 ? f input supply voltage ramp-up time 0 to 4.3v 40 ? ? s table 43. ldo3p3 specifications specification notes min. typ. max. units input supply voltage, v in min. = v o + 0.2v = 3.5v dropout voltage requirement must be met under maximum load for performance specifications. 3.1 3.6 4.8 a v output current ? 0.001 ? 450 ma nominal output voltage, v o default = 3.3v. ? 3.3 ? v dropout voltage at max. load. ? ? 200 mv
document no. 002-14797 rev. *h page 108 of 128 cyw4343x 19.3 cldo output voltage dc accuracy includes line/load regulation. ?5 ? +5 % quiescent current no load ? 66 85 a line regulation v in from (v o + 0.2v) to 4.8v, max. load ? ? 3.5 mv/v load regulation load from 1 ma to 450 ma ? ? 0.3 mv/ma psrr v in v o + 0.2v, v o = 3.3v, c o = 4.7 f, max. load, 100 hz to 100 khz 20 ? ? db ldo turn-on time chip already powered up. ? 160 250 s external output capacitor, c o ceramic, x5r, 0402, (esr: 5 m ? ?240 m ? ), 10%, 10v 1.0 b 4.7 5.64 f external input capacitor for sr_vddbata5v pin (shared with band gap) ceramic, x5r, 0402, (esr: 30m-200 m ? ), 10%, 10v. not needed if sharing vbat capacitor 4.7 f with sr_vddbatp5v. ?4.7?f a. the maximum continuous voltage is 4.8v. voltages up to 6.0v for up to 10 seconds, cumulative duration, over the lifetime of t he device are allowed. voltages as high as 5.0v for up to 250 seconds, cumu lative duration, over the lifetime of the device are allowed. b. minimum capacitor value refers to the re sidual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. table 44. cldo specifications specification notes min. typ. max. units input supply voltage, v in min. = 1.2 + 0.15v = 1.35v dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 v output current ? 0.2 ? 200 ma output voltage, v o programmable in 10 mv steps. default = 1.2.v 0.95 1.2 1.26 v dropout voltage at max. load ? ? 150 mv output voltage dc accuracy includes line/load regulation ?4 ? +4 % quiescent current no load ? 13 ? a 200 ma load ? 1.24 ? ma line regulation v in from (v o + 0.15v) to 1.5v, maximum load ??5mv/v load regulation load from 1 ma to 300 ma ? 0.02 0.05 mv/ma leakage current power down ? 5 20 a bypass mode ? 1 3 a psrr @1 khz, vin 1.35v, c o = 4.7 f 20 ? ? db start-up time of pmu vddio up and steady. time from the reg_on rising edge to the cldo reaching 1.2v. ? ? 700 s ldo turn-on time ldo turn-on time when rest of the chip is up. ? 140 180 s external output capacitor, c o total esr: 5 m ? ?240 m ? 1.1 a a. minimum capacitor value refers to the re sidual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 2.2 ? f external input capacitor only use an external input capacitor at the vdd_ldo pin if it is not supplied from cbuck output. ?12.2f table 43. ldo3p3 specifications (cont.) specification notes min. typ. max. units
document no. 002-14797 rev. *h page 109 of 128 cyw4343x 19.4 lnldo table 45. lnldo specifications specification notes min. typ. max. units input supply voltage, vin min. v in = v o + 0.15v = 1.35v (where v o = 1.2v) dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 v output current ? 0.1 ? 150 ma output voltage, v o programmable in 25 mv steps. default = 1.2v 1.1 1.2 1.275 v dropout voltage at maximum load ? ? 150 mv output voltage dc accuracy includes line/load regulation ?4 ? +4 % quiescent current no load ? 10 12 a max. load ? 970 990 a line regulation v in from (v o + 0.15v) to 1.5v, 200 ma load ?? 5mv/v load regulation load from 1 ma to 200 ma: v in (v o + 0.12v) ? 0.025 0.045 mv/ma leakage current power-down, junction temp. = 85c ? 5 20 a output noise @30 khz, 60?150 ma load c o = 2.2 f @100 khz, 60?150 ma load c o = 2.2 f ? ? 60 35 ? psrr @1 khz, v in (v o + 0.15v), c o = 4.7 f 20 ? ? db ldo turn-on time ldo turn-on time when rest of chip is up ? 140 180 s external output capacitor, c o total esr (trace/capacitor): 5 m ? ?240 m ? 0.5 a a. minimum capacitor value refers to the re sidual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 2.2 4.7 f external input capacitor only use an exte rnal input capacitor at the vdd_ldo pin if it is not supplied from cbuck output. total esr (trace/capacitor): 30 m ? ?200 m ? ? 1 2.2 f nv/ hz
document no. 002-14797 rev. *h page 110 of 128 cyw4343x 20. system power consumption note: the values in this data sheet are design goals and are subjec t to change based on device characterization.unless otherwise stated, these values apply for the conditions specified in table 30, ?recommended operating condi tions and dc characteristics,? on page 91 . 20.1 wlan current consumption table 46 shows typical currents consumed by the cyw4343x?s wlan section. all values s hown are with the bluetooth core in reset mode with bluetooth and fm off. 20.1.1 2.4 ghz mode table 46. 2.4 ghz mode wlan power consumption mode rate vbat = 3.6v, vddio = 1.8v, ta 25c vbat (ma) vio (a) sleep modes leakage (off) n/a 0.0035 0.08 sleep (idle, unassociated) a a. device is initialized in sleep mode, but not associated. n/a 0.0058 80 sleep (idle, associated, inter-beacons) b b. device is associated, and then enters power save mode (idle between beacons). rate 1 0.0058 80 ieee power save pm1 dtim1 (avg.) c c. beacon interval = 100 ms; beacon duration = 1 ms @ 1 mbps (integrated sleep + wakeup + beacon). rate 1 1.05 74 ieee power save pm1 dtim3 (avg.) d d. beacon interval = 300 ms; beacon duration = 1 ms @ 1 mbps (integrated sleep + wakeup + beacon). rate 1 0.35 86 ieee power save pm2 dtim1 (avg.) c rate 1 1.05 74 ieee power save pm2 dtim3 (avg.) d rate 1 0.35 86 active modes rx listen mode e e. carrier sense (cca) when no carrier present. n/a 37 12 rx active (at ?50dbm rssi) f f. tx output power is measured on the chip-out side; duty cycle =1 00%. tx active mode is measured in packet engine mode (pseudo- random data) rate 1 39 12 rate 11 40 12 rate 54 40 12 rate mcs7 41 12 tx f rate 1 @ 20 dbm 320 15 rate 11 @ 18 dbm 290 15 rate 54 @ 15 dbm 260 15 rate mcs7 @ 15 dbm 260 15
document no. 002-14797 rev. *h page 111 of 128 cyw4343x 20.2 bluetooth and fm current consumption the bluetooth, ble, and fm current c onsumption measurements are shown in table 47 . note: the wlan core is in reset (wlan_reg_on = low) for all measurements provided in ta b l e 4 7 . for fm measurements, the bluetooth core is in sleep mode. the bt current consumption num bers are measured based on gf sk tx output power = 10 dbm. table 47. bluetooth ble and fm current consumption operating mode vbat (vbat = 3.6v) typical vddio (vddio = 1.8v) typical units sleep 6 150 a standard 1.28s inquiry scan 193 162 a 500 ms sniff master 305 172 a dm1/dh1 master 23.3 ? ma dm3/dh3 master 28.4 ? ma dm5/dh5 master 29.1 ? ma 3dh5/3dh5 master 25.1 ? ma sco hv3 master 11.8 ? ma fmrx analog audio only a a. in mono/stereo blend mode. 8.6 ? ma fmrx i 2 s audio a 8? ma fmrx i 2 s audio + rds a 8? ma fmrx analog audio + rds a 8.6 ? ma ble scan b b. no devices present. a 1.28 second interval with a scan window of 11.25 ms. 187 164 a ble adv. ? unconnectable 1.00 sec 93 163 a ble connected 1 sec 71 163 a
document no. 002-14797 rev. *h page 112 of 128 cyw4343x 21. interface timing and ac characteristics note: values in this data sheet are design goals and are subject to change based on the results of device characterization. unless otherwise stated, the specifications in this section apply when the operating c onditions are within the limits specified in table 28 on page 90 and table 30 on page 91 . functional operation outside of these limits is not guaranteed. 21.1 sdio default mode timing sdio default mode timing is shown by the combination of figure 51 and table 48 on page 113 . figure 51. sdio bus timing (default mode) t wl t wh f pp t thl t isu t tlh t ih t odly (max) t odly (min) input output sdio_clk
document no. 002-14797 rev. *h page 113 of 128 cyw4343x 21.2 sdio high-speed mode timing sdio high-speed mode timing is shown by the combination of figure 52 and table 49 . figure 52. sdio bus timing (high-speed mode) table 48. sdio bus timing a parameters (default mode) a. timing is based on cl ? 40 pf load on command and data. parameter symbol minimum typical maximum unit sdio clk (all values are referred to minimum vih and maximum vil b ) b. min(vih) = 0.7 vddio and max(vil) = 0.2 vddio. frequency?data transfer mode fpp 0 ? 25 mhz frequency?identification mode fod 0 ? 400 khz clock low time twl 10 ? ? ns clock high time twh 10 ? ? ns clock rise time ttlh ? ? 10 ns clock fall time tthl ? ? 10 ns inputs: cmd, dat (referenced to clk) input setup time tisu 5??ns input hold time tih 5??ns outputs: cmd, dat (referenced to clk) output delay time?data transfer mode todly 0 ? 14 ns output delay time?identification mode todly 0 ? 50 ns t wl t wh f pp t thl t isu t tlh t ih t odly input output 50% vdd t oh sdio_clk
document no. 002-14797 rev. *h page 114 of 128 cyw4343x 21.3 gspi signal timing the gspi device always samples data on the rising edge of the clock. figure 53. gspi timing table 49. sdio bus timing a parameters (h igh-speed mode) a. timing is based on cl ? 40 pf load on command and data. parameter symbol minimum typical maximum unit sdio clk (all values are referred to minimum vih and maximum vil b ) b. min(vih) = 0.7 vddio and max(vil) = 0.2 vddio. frequency ? data transfer mode fpp 0 ? 50 mhz frequency ? identification mode fod 0 ? 400 khz clock low time twl7??ns clock high time twh7??ns clock rise time ttlh??3ns clock fall time tthl??3ns inputs: cmd, dat (referenced to clk) input setup time tisu 6??ns input hold time tih 2??ns outputs: cmd, dat (referenced to clk) output delay time ? data transfer mode todly ? ? 14 ns output hold time toh 2.5 ? ? ns total system capacitance (each line) cl ? ? 40 pf table 50. gspi ti ming parameters parameter symbol minimum maximum units note clock period t1 20.8 ? ns f max = 50 mhz clock high/low t2/t3 (0.45 t1) ? t4 (0.55 t1) ? t4 ns ? clock rise/fall ti me t4/t5 ? 2.5 ns ? t4 t5 t1 t2 t 3 t7 t6 t9 t8 spi_clk spi_din spi_dout (falling ? edge)
document no. 002-14797 rev. *h page 115 of 128 cyw4343x 21.4 jtag timing input setup time t6 5.0 ? ns setup time, simo valid to spi_clk active edge input hold time t7 5.0 ? ns hold time, spi_clk active edge to simo invalid output setup time t8 5.0 ? ns setup time, somi valid before spi_clk rising output hold time t9 5.0 ? ns hold time, spi_clk active edge to somi invalid csx to clock a ? 7.86 ? ns csx fall to 1st rising edge clock to csx c ? ? ? ns last falling edge to csx high a. spi_csx remains active for entire duration of gspi read/wri te/write_read transaction (that is, overall words for multiple wor d transaction) table 51. jtag timing characteristics signal name period output maximum output minimum setup hold tck 125 ns ? ? ? ? tdi ? ? ? 20 ns 0 ns tms ? ? ? 20 ns 0 ns tdo ? 100 ns 0 ns ? ? jtag_trst 250 ns ? ? ? ? table 50. gspi timing parameters (cont.) parameter symbol minimum maximum units note
document no. 002-14797 rev. *h page 116 of 128 cyw4343x 22. power-up sequence and timing 22.1 sequencing of reset and regulator control signals the cyw4343x has two signals that allow the host to control powe r consumption by enabling or disabling the bluetooth, wlan, and internal regulator blocks. these signals are described below. additionally, di agrams are provided to i ndicate pro per sequen cing of the signals for various operational states (see figure 54 on page 116 through figure 57 on page 117 ). the timing values indicated are minimum required values; longer delays are also acceptable. note: the wl_reg_on and bt_reg_on signals are or?ed in the cy w4343x. the diagrams show both signals going high at the same time (as would be the case if both reg signals we re controlled by a single host gpio). if two independent host gpios are used (one for wl_reg_on and one for bt_reg_on), then only one of the two signals needs to be high to enable the cyw4343x regulators. the reset requirements for the bluetooth core are also applicable for the fm core. in other words, if fm is to be used, then the bluetooth core must be enabled. the cyw4343x has an internal power-on reset (por) circuit. the device will be held in reset for a maximum of 110 ms after vddc and vddio have both passed the por threshold (s ee table 30, ?recommended operating conditions and dc characteristics,? on page 91). wait at least 150 ms after vddc and vddio are available before initiating sdio accesses. vbat and vddio should not rise faster than 40 s. vbat shoul d be up before or at the same time as vddio. vddio should not be present first or be held high before vbat is high. 22.1.1 description of control signals wl_reg_on : used by the pmu to power up the wlan section. it is also or-gated with the bt_reg_on input to control the internal cyw4343x regulators. when this pin is high, t he regulators are enabled and the wlan section is out of reset. when this pin is low the wlan section is in reset. if both the bt_reg_on and wl_reg_on pins are low, the regulators are disabled. bt_reg_on : used by the pmu (or-gated with wl_reg_on) to power up the internal cyw4343x regulators. if both the bt_reg_on and wl_reg_on pins are low, the regulators are disabled. when this pin is low and wl_reg_on is high, the bt section is in reset. note: for both the wl_reg_on and bt_reg_on pins, there should be at least a 10 ms time delay between consecutive toggles (where both signals have been driven low). this is to allow time for the cbuck regula tor to discharge. if th is delay is not fol lowed, then there may be a vddio in-rush current on th e order of 36 ma during the next pmu cold start. 22.1.2 control sign al timing diagrams figure 54. wlan = on, bluetooth = on 32.678 khz sleep clock vbat vddio wl_reg_on bt_reg_on 90% of vh ~ 2 sleep cycles
document no. 002-14797 rev. *h page 117 of 128 cyw4343x figure 55. wlan = off, bluetooth = off figure 56. wlan = on, bluetooth = off figure 57. wlan = off, bluetooth = on 32.678 khz sleep clock vbat vddio wl_reg_on bt_reg_on 32.678 khz sleep clock vbat vddio wl_reg_on bt_reg_on 90% of vh ~ 2 sleep cycles 32.678 khz sleep clock vbat vddio wl_reg_on bt_reg_on 90% of vh ~ 2 sleep cycles
document no. 002-14797 rev. *h page 118 of 128 cyw4343x 23. package information 23.1 package thermal characteristics 23.1.1 junction temperature estimation and psi versus theta jc package thermal characterization parameter psi-jt ( ? jt ) yields a better estimation of actual junction temperature (t j ) versus using the junction-to-case thermal resistance parameter theta-j c ( ? jc ). the reason for this is ? jc assumes that all the power is dissipated through the top surface of the package case . in actual applications, some of the powe r is dissipated through the bottom and sid es of the package. ? jt takes into account power dissipated through the top, bo ttom, and sides of the package. the equation for calculat- ing the device junction tem perature is as follows: t j = t t + p ?? jt where: t j = junction temperature at steady-state condition, c t t = package case top center temperat ure at steady-state condition, c p = device power dissipation, watts ? jt = package thermal characteristics (no airflow), c/w table 52. package thermal characteristics a a. no heat sink, ta = 70c. this is an estimate based on a 4-layer pcb that conforms to eia/jesd51?7 (101.6 mm x 114.3 mm x 1.6 mm) and p = 1.2w continuous dissipation. characteristic value in still air ? ja (c/w) 53.11 54.75 ? jb (c/w) 13.14 15.38 ? jc (c/w) 6.36 7.16 ? jt (c/w) 0.04 ? jb (c/w) 14.21 maximum junction temperature t j (c) b b. absolute junction temperature limits maintained through acti ve thermal monitoring and dy namic tx duty cycle limiting. 125 maximum power dissipation (w) 1.2
document no. 002-14797 rev. *h page 119 of 128 cyw4343x 24. mechanical information figure 58 shows the mechanical drawing for the cyw4343x wlbga package. figure 58. 74-ball wlbga mechanical information
document no. 002-14797 rev. *h page 120 of 128 cyw4343x figure 59 shows the mechanical drawing for the cyw4343x wlbga package. figure 59. 63-ball wlbga mechanical information
document no. 002-14797 rev. *h page 121 of 128 cyw4343x figure 60 shows the mechanical drawing for the cyw4343x wlcsp package. figure 61 shows the wlcsp keep-out areas. figure 60. 153-bump wlcsp mechanical information
document no. 002-14797 rev. *h page 122 of 128 cyw4343x note: no top-layer metal is allowed in the keep-out areas. note: a dxf file containing wlbga keep-outs can be imported into a la yout program. contact your cypress fae for more information.[ figure 61. wlcsp package keep-out areas?top view with the bumps facing down
document no. 002-14797 rev. *h page 123 of 128 cyw4343x figure 62. wlbga package keep-out areas?top view with the bumps facing down
document no. 002-14797 rev. *h page 124 of 128 cyw4343x figure 63. wlbga package keep-out areas? top view with the bumps facing down[
document no. 002-14797 rev. *h page 125 of 128 cyw4343x 25. ordering information table 53. part ordering information part number a a. add ?t? to the end of the part number to specify ?tape and reel.? package description operating ambient temperature CYW4343SKUBG 74-ball wlbga halogen-free package (4.87 mm x 2.87 mm, 0.40 pitch) 2.4 ghz single-band wlan ieee 802.11n + bt 4.1 + fmrx ?30c to +70c cyw4343wkubg 74-ball wlbga halogen-free package (4.87 mm x 2.87 mm, 0.40 pitch) 2.4 ghz single-band wlan ieee 802.11n + bt 4.1 + fmrx + wireless charging ?30c to +70c cyw4343wkwbg 153-bump wlcsp 2.4 ghz single-band wlan ieee 802.11n + bt 4.1 + fmrx + wireless charging ?30c to +70c cyw4343w1kubg 74-ball wlbga halogen-free package (4.87 mm x 2.87 mm, 0.40 pitch) 2.4 ghz single-band wlan ieee 802.11n + bt 4.1 + fmrx + wireless charging ?30c to +70c
document no. 002-14797 rev. *h page 127 of 128 cyw4343x 1 document history page document title: cyw4343x sing le-chip ieee 802.11 b/g/n mac/ baseband/radio with bluetoot h 4.1, an fm receiver, and wireless charging document number: 002-14797 revision ecn orig. of change submission date description of change ** ? ? 03/10/14 4343w-ds100-r initial release *a to *f ?? 04/08/2014 to 07/01/2015 (4343w-ds101-r 4343w-ds102-r 4343w-ds103-r 4343w-ds104-r 4343w-ds105-r 4343w-ds106-r) updated: table 26, ?i/o states,? on page 87. table 29, ?esd specifications,? on page 90. table 32, ?wlan 2.4 ghz receiver pe rformance specifications,? on page 92. table 33, ?wlan 2.4 ghz transmitter pe rformance specifications,? on page 95. table 41, ?fm receiver specifications,? on page 103. table 46, ?2.4 ghz mode wlan power consumption,? on page 110. [4343w]table 53, ?part ordering information,? on page 125 . *g ? utsv 08/24/15 4343w-ds107-r updated: figure 5: ?typical power topology (1 of 2)(4343s),? on page 12figure 6: ?typical power topology (1 of 2)(4343w+43cs4343w1),? on page 13 figure 7: ?typical power topology (1 of 2),? on page 14 and [4343s]figure 8: ?typical power topology (2 of 2)(4343s),? on page 15[4343w+43cs4343w1]figure 9: ?typical power topology (2 of 2)(4343w+43cs4343w1),? on page 16 figure 10: ?typical power topology (2 of 2),? on page 17. table 3, ?crystal oscillator and exter nal clock requirements and performance,? on page 23. table 26, ?i/o states,? on page 87. *h 5445248 utsv 10/19/2016 migrated to cypress template format added cypress part numbering scheme 1.
document no. 002-14797 rev. *h revised october 19, 2016 page 128 of 128 cyw4343x ? cypress semiconductor corporation, 2014-2016. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hard ware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modi fication, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the im plied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly desig n, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear in stallations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("unintended us es"). a critical component is any compo nent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. cypress is not liable, in who le or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cy press harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete lis t of cypress trademarks, visit cypress.com. other names and bra nds may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community forums | wiced iot forum | projects | video | blogs | training components technical support cypress.com/support 128

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